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[97.113.2.170]) by smtp.gmail.com with ESMTPSA id e18-v6sm3495636pfi.100.2018.05.10.20.52.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 20:52:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 10 May 2018 20:52:35 -0700 Message-Id: <20180511035240.4016-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180511035240.4016-1-richard.henderson@linaro.org> References: <20180511035240.4016-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::244 Subject: [Qemu-devel] [PATCH 4/9] target/riscv: Introduce cpu_riscv_get_fcsr X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Michael Clark , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Cc: Michael Clark Cc: Palmer Dabbelt Cc: Sagar Karandikar Cc: Bastian Koppelmann Signed-off-by: Richard Henderson --- target/riscv/cpu.h | 1 + target/riscv/fpu_helper.c | 6 ++++++ target/riscv/op_helper.c | 3 +-- 3 files changed, 8 insertions(+), 2 deletions(-) -- 2.17.0 Reviewed-by: Philippe Mathieu-Daudé diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 34abc383e3..f2bc243b95 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -265,6 +265,7 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env, uint32_t exception, uintptr_t pc); target_ulong cpu_riscv_get_fflags(CPURISCVState *env); +target_ulong cpu_riscv_get_fcsr(CPURISCVState *env); void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong); #define TB_FLAGS_MMU_MASK 3 diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index abbadead5c..41c7352115 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -37,6 +37,12 @@ target_ulong cpu_riscv_get_fflags(CPURISCVState *env) return hard; } +target_ulong cpu_riscv_get_fcsr(CPURISCVState *env) +{ + return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT) + | (env->frm << FSR_RD_SHIFT); +} + void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard) { int soft = 0; diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 3abf52453c..fd2d8c0a9d 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -423,8 +423,7 @@ target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) return env->frm; case CSR_FCSR: validate_mstatus_fs(env, GETPC()); - return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT) - | (env->frm << FSR_RD_SHIFT); + return cpu_riscv_get_fcsr(env); /* rdtime/rdtimeh is trapped and emulated by bbl in system mode */ #ifdef CONFIG_USER_ONLY case CSR_TIME: