From patchwork Thu May 10 09:42:06 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 135398 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp783761lji; Thu, 10 May 2018 02:44:46 -0700 (PDT) X-Google-Smtp-Source: AB8JxZqA7XBY7Tff9w7xORcaWRtmdLO504ntFKeSs1+2tVTW65Dmk93by02FdwajAboagFRvI33q X-Received: by 2002:ac8:36d1:: with SMTP id b17-v6mr603867qtc.148.1525945486035; Thu, 10 May 2018 02:44:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525945486; cv=none; d=google.com; s=arc-20160816; b=TjZ/E1K62TG4C53HIVHWCTUzQtvVBteTy2cd7N9YvCMAEnq/qudWzysd9iIph4cIg5 fgm0SZD5hsSocVHcj/DzqjIN+7BQsB4LOHT+Vs6No3+68KG4AhaGaS6NKXjwrIK2YUXD KBW7uKoibG+ug8o0zKC+GCwKyJqFoCuaUJQck1W0n8/3fMzEOnelKc+mT1Q0gfU1mag4 ujYqDGri2eHVWEmI5a3xgMCeNOvL24aLDqo0GnCv2O1uxk+Xp+9Q3z72fSPiZABVZOuH ooO9pl9NXtwbtx3gY5GIX76MEmi94BA5tCmlRXvZL3QG3pNY+8I7ktFFW5QY2BOnrE9g PONA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=1hajm0U+qnqFDGdJa0m1m0J/D5ufKVQ+/rQlp0BRUVA=; b=OVSVZzlyr1ZZ/TW3plDnd/zjyBxvspSHYJ5QmhPg7iu/iKAe95X4xys4N8AkCk7Wps e0rhXndiZc3TK5lZltlZGZJm/YDcTWEKuuNepINdI86eadvsX5QPsktNwLaYmkOt/KG+ wbvDFbP8++aTKsrlp+TUawloYw84+xDskWpY5bA7fVAV4ydeR3+U6w/RUb+i6zTXJoUU Lkg5/XIldXpCCEaNipUgn2ZohHGM1Ge/mSIe8T1gUp7Sk4colEE1G1pbzZDJiSgxBrPv IlCdNTKHGY/+obhR50lUZddUNI/rx2wUbjG3EaFHxdoLqcKxP0n4wsRZCUamxmzDfVOA cCfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MdGcWO+o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id q6-v6si384852qtl.131.2018.05.10.02.44.45 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 10 May 2018 02:44:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MdGcWO+o; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:60995 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGi7x-0005ix-8s for patch@linaro.org; Thu, 10 May 2018 05:44:45 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46181) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fGi5W-0002FW-Nq for qemu-devel@nongnu.org; Thu, 10 May 2018 05:42:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fGi5V-0004UI-Hz for qemu-devel@nongnu.org; Thu, 10 May 2018 05:42:14 -0400 Received: from mail-wm0-x244.google.com ([2a00:1450:400c:c09::244]:38218) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fGi5V-0004Tl-9k for qemu-devel@nongnu.org; Thu, 10 May 2018 05:42:13 -0400 Received: by mail-wm0-x244.google.com with SMTP id y189-v6so3199508wmc.3 for ; Thu, 10 May 2018 02:42:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1hajm0U+qnqFDGdJa0m1m0J/D5ufKVQ+/rQlp0BRUVA=; b=MdGcWO+oFGTYGimjrD40A+YqnghQGMKcft9IoYTWrIR2Ip1daNS2mZOB5me0amPr5A x1OvSCSX8Qfxo3uGcEFEKmAUBeUrHBFCI6VwVcA3y1pHPNXNdWqdl52bYWVAvIJ16R3P 9+AE1grYX/3Qg8bQUH+31Cc6+9GkH0ieFx6q4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1hajm0U+qnqFDGdJa0m1m0J/D5ufKVQ+/rQlp0BRUVA=; b=NAvYyy6cOkF+tPyo/FXB9nERdYIVbURmj1iz7SbwyUe2U77hUlvwjsi488qXriatIk Y9RkWjrN2Dr7IuFDmEBOxMif6ieJiYORJXDh5ho/pNXyZJ9m3FHHGcuV4eoNxGs6wtD3 /MF8i+rohZNqyBUn8wfPLql1L99CTTLXojJatXr/xy4SmfmnDmHBiUmFs+M3FrgrrQ1R xzb/GxFrK8+vlDQKS2Fp2lHgls4ihnDB1ml0VePgbINbqf5EKpzp69pXpePuzL9PYCOC QfnSQlx7RnD8CkpdqKCg545lfjcltfSyhCQSDN8wAom2O3NpScZ5V5LZAOS7dK67lo0f EeVQ== X-Gm-Message-State: ALKqPwdDFfnP6V3GWMjwaZhFn0e5UWVRsQavX6D5iPnNBwTNI6JA74Zt YtxPr34LgTrA0WTQbm4THikVThzgQcg= X-Received: by 2002:a1c:2084:: with SMTP id g126-v6mr838578wmg.52.1525945332151; Thu, 10 May 2018 02:42:12 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id f10-v6sm476056wmc.0.2018.05.10.02.42.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 10 May 2018 02:42:08 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 59C1C3E04F4; Thu, 10 May 2018 10:42:07 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Thu, 10 May 2018 10:42:06 +0100 Message-Id: <20180510094206.15354-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180510094206.15354-1-alex.bennee@linaro.org> References: <20180510094206.15354-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c09::244 Subject: [Qemu-devel] [PATCH v3 5/5] target/arm: squash FZ16 behaviour for conversions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The ARM ARM specifies FZ16 is suppressed for conversions. Rather than pushing this logic into the softfloat code we can simply save the FZ state and temporarily disable it for the softfloat call. Signed-off-by: Alex Bennée --- target/arm/helper.c | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) -- 2.17.0 diff --git a/target/arm/helper.c b/target/arm/helper.c index 4dd28bb70c..17147be58b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11459,12 +11459,20 @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env) /* Half precision conversions. */ static float32 do_fcvt_f16_to_f32(float16 a, float_status *s, bool ahp) { - return float16_to_float32(a, !ahp, s); + flag save_flush_to_zero = s->flush_to_zero; + set_flush_to_zero(false, s); + float32 r = float16_to_float32(a, !ahp, s); + set_flush_to_zero(save_flush_to_zero, s); + return r; } static float16 do_fcvt_f32_to_f16(float32 a, float_status *s, bool ahp) { - return float32_to_float16(a, !ahp, s); + flag save_flush_to_zero = s->flush_to_zero; + set_flush_to_zero(false, s); + float16 r = float32_to_float16(a, !ahp, s); + set_flush_to_zero(save_flush_to_zero, s); + return float16_val(r); } float32 HELPER(neon_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode) @@ -11494,13 +11502,21 @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode) float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode) { float_status *fpst = fpstp; - return float16_to_float64(a, !ahp_mode, fpst); + flag save_flush_to_zero = fpst->flush_to_zero; + set_flush_to_zero(false, fpst); + float64 r = float16_to_float64(a, !ahp_mode, fpst); + set_flush_to_zero(save_flush_to_zero, fpst); + return r; } float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode) { float_status *fpst = fpstp; - return float64_to_float16(a, !ahp_mode, fpst); + flag save_flush_to_zero = fpst->flush_to_zero; + set_flush_to_zero(false, fpst); + float16 r = float64_to_float16(a, !ahp_mode, fpst); + set_flush_to_zero(save_flush_to_zero, fpst); + return float16_val(r); } #define float32_two make_float32(0x40000000)