From patchwork Tue May 8 15:14:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 135177 Delivered-To: patch@linaro.org Received: by 10.46.151.6 with SMTP id r6csp4513509lji; Tue, 8 May 2018 08:17:40 -0700 (PDT) X-Google-Smtp-Source: AB8JxZoM3iYKnSvH2SQQliz1PFes6Mr1F8r8ODeVxGIubmbDuFxJJ+2iI2ovFrQ6hPAheqJxNuQS X-Received: by 2002:aed:3641:: with SMTP id e59-v6mr12423068qtb.341.1525792660361; Tue, 08 May 2018 08:17:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1525792660; cv=none; d=google.com; s=arc-20160816; b=rPXQx9f81V3Ok+A4ZIsz5SIvsghQ6djRHd6cY9sK6bqpLSuxaFKuauPW6G3GRvRm0t 50XSTm1DLB0KZ1H6gO98HVOs1MOoJCg8BGbJyEaqShycsNW5mBhmw9w0jaxQ4wL7PGeT QDYsZnFt+GXZET84U1kJkANtLvINvD9XXRb9L0tIjTBsVffiq4NlQKmP/haeLYCRZaPd S6PGhTu78EabXiHRaGK9+KoZPUBhSp3O2LNfmEKZONz1+pUFGu15ga93gHFI4NSxOmaw yq/SJA2i/CIbqjymDWiJZ1sRhQqGk4Cek0PZVvYcjImTh556aiMihwMxb2+L4G9760pY QtuQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=aE6V3PiTSNNT++yQIFfjD934zl2l9CsEY3U24eKhdTs=; b=N/ZZK0smgApjkB2BmcU/Nog97n/Xe9Go+gno+WFtO+PpalqdOKEAwDhzRud/jRaBGq dPInk39ss0eb6c+hSVlnFF1p1fVxhj6/cxQ2fqX24Z+muFx8oYSn6f5/IfGDwvTFD9q0 NN+bA+qTiMTHcsScq95or1fWGr4m5ScrrLGCIAkYs8CGlXM6mX2KSeICpFIKkMH6+A3a Y0A21CYeSVg8BS/jWfBfTmDyl/PnDGT4/2b9giS8coPeJRq0f2LJfJe2jZhXePETotJB 2t4Its7IF0ktZB31BHLvfqCpo7ZzMyAiK+UusVyI43LWawh2z6LVM4wp7TYg0Q9wNWf9 LBqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=etEpoO50; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f16-v6si2028000qvm.80.2018.05.08.08.17.40 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 08 May 2018 08:17:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=etEpoO50; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:51816 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG4N1-00005D-O2 for patch@linaro.org; Tue, 08 May 2018 11:17:39 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59475) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fG4KC-0006Xe-Ua for qemu-devel@nongnu.org; Tue, 08 May 2018 11:14:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fG4KA-00085k-8O for qemu-devel@nongnu.org; Tue, 08 May 2018 11:14:44 -0400 Received: from mail-pg0-x242.google.com ([2607:f8b0:400e:c05::242]:46991) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fG4KA-00085A-3M for qemu-devel@nongnu.org; Tue, 08 May 2018 11:14:42 -0400 Received: by mail-pg0-x242.google.com with SMTP id z4-v6so21298088pgu.13 for ; Tue, 08 May 2018 08:14:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=aE6V3PiTSNNT++yQIFfjD934zl2l9CsEY3U24eKhdTs=; b=etEpoO500Zx1Ji2czEnjGQDQluhfJVJALZ3TqGGwT1KbsPHeJ5nt3zlvKQrktnoZ7r 6XoWdeg2Q06qAjqRQRkd6Z43t8tPI8X5dpmkqmeiZefF69g2hIDSWsa/1P4pKdZ8xplx 05wh46RraBSnFl+in2C1KWyhIVC50HqA9hDBU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=aE6V3PiTSNNT++yQIFfjD934zl2l9CsEY3U24eKhdTs=; b=Kx1BF3h03ZHjD+DazYRiLQZ3SCxuvugo5pF/M4P37DDokAk4RNBRfw92eJasj7YmUo KsoEMBbZfu+y3FYOo97WalN0wOshh1AxNiFtgQYQuKxsgraiHROMIFSFcg9N2ceK0C7q TcgtCe29RZSrLhsHI4AkGbMS6bMdfn7uJg+u1BmKvuvUyG7SZk3+SVwJsdYNslRA55iT HWAdofcr3q/PLp4QGyz3b2zXiOGVWYSDJ4fpl0lLZqOTGk90rIGorL5xFDXhDDWGwhS4 K04PQIq6/6Tnc5Jr9D7setFm8znrEZgJnk/srDRElquof7H9DDDOISGz87BbuD/+04M1 +AfQ== X-Gm-Message-State: ALQs6tD4qvVpijqGWfyS1UhhuCKJd5pven/PaJdM8F9HzltOsj9bQAEe YZ6YUlzBWziIwexrjP7LV2goTGudQhw= X-Received: by 10.98.157.137 with SMTP id a9mr40253017pfk.206.1525792480839; Tue, 08 May 2018 08:14:40 -0700 (PDT) Received: from cloudburst.twiddle.net (97-113-2-170.tukw.qwest.net. [97.113.2.170]) by smtp.gmail.com with ESMTPSA id n10sm55598896pfj.68.2018.05.08.08.14.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 May 2018 08:14:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 8 May 2018 08:14:28 -0700 Message-Id: <20180508151437.4232-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180508151437.4232-1-richard.henderson@linaro.org> References: <20180508151437.4232-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::242 Subject: [Qemu-devel] [PATCH v3 01/10] tcg: Introduce helpers for integer min/max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These operations are re-invented by several targets so far. Several supported hosts have insns for these, so place the expanders out-of-line for a future introduction of tcg opcodes. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/tcg-op.h | 16 ++++++++++++++++ tcg/tcg-op.c | 40 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) -- 2.17.0 diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 5d2c91a1b6..0451e2752e 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -324,6 +324,10 @@ void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg); void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); static inline void tcg_gen_discard_i32(TCGv_i32 arg) { @@ -517,6 +521,10 @@ void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg); void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); #if TCG_TARGET_REG_BITS == 64 static inline void tcg_gen_discard_i64(TCGv_i64 arg) @@ -1025,6 +1033,10 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 #define tcg_gen_muls2_tl tcg_gen_muls2_i64 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 +#define tcg_gen_smin_tl tcg_gen_smin_i64 +#define tcg_gen_umin_tl tcg_gen_umin_i64 +#define tcg_gen_smax_tl tcg_gen_smax_i64 +#define tcg_gen_umax_tl tcg_gen_umax_i64 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 @@ -1123,6 +1135,10 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 #define tcg_gen_muls2_tl tcg_gen_muls2_i32 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 +#define tcg_gen_smin_tl tcg_gen_smin_i32 +#define tcg_gen_umin_tl tcg_gen_umin_i32 +#define tcg_gen_smax_tl tcg_gen_smax_i32 +#define tcg_gen_umax_tl tcg_gen_umax_i32 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 34b96d68f3..5b82c3be8d 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1033,6 +1033,26 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) } } +void tcg_gen_smin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, a, b); +} + +void tcg_gen_umin_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, a, b); +} + +void tcg_gen_smax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_movcond_i32(TCG_COND_LT, ret, a, b, b, a); +} + +void tcg_gen_umax_i32(TCGv_i32 ret, TCGv_i32 a, TCGv_i32 b) +{ + tcg_gen_movcond_i32(TCG_COND_LTU, ret, a, b, b, a); +} + /* 64-bit ops */ #if TCG_TARGET_REG_BITS == 32 @@ -2438,6 +2458,26 @@ void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) tcg_temp_free_i64(t2); } +void tcg_gen_smin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, a, b); +} + +void tcg_gen_umin_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, a, b); +} + +void tcg_gen_smax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_movcond_i64(TCG_COND_LT, ret, a, b, b, a); +} + +void tcg_gen_umax_i64(TCGv_i64 ret, TCGv_i64 a, TCGv_i64 b) +{ + tcg_gen_movcond_i64(TCG_COND_LTU, ret, a, b, b, a); +} + /* Size changing operations. */ void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg)