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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id u14si3056013qtc.61.2018.04.06.08.24.13 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 06 Apr 2018 08:24:14 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:34060 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f4TDp-0000JG-Cx for patch@linaro.org; Fri, 06 Apr 2018 11:24:13 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32915) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1f4T9E-0004j3-3w for qemu-devel@nongnu.org; Fri, 06 Apr 2018 11:19:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1f4T97-0004pX-Ld for qemu-devel@nongnu.org; Fri, 06 Apr 2018 11:19:28 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:21758 helo=mx07-00178001.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1f4T97-0004p0-Bw for qemu-devel@nongnu.org; Fri, 06 Apr 2018 11:19:21 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w36FF9s8018376; Fri, 6 Apr 2018 17:19:20 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2h1yf7prcq-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Fri, 06 Apr 2018 17:19:20 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5B88431; Fri, 6 Apr 2018 15:19:19 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node1.st.com [10.75.127.13]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 49049A6EC; Fri, 6 Apr 2018 15:19:19 +0000 (GMT) Received: from gnx2104.gnb.st.com (10.75.127.51) by SFHDAG5NODE1.st.com (10.75.127.13) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Fri, 6 Apr 2018 17:19:18 +0200 From: Christophe Lyon To: , , Date: Fri, 6 Apr 2018 17:17:32 +0200 Message-ID: <20180406151752.10854-5-christophe.lyon@st.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20180406151752.10854-1-christophe.lyon@st.com> References: <20180406151752.10854-1-christophe.lyon@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.51] X-ClientProxiedBy: SFHDAG6NODE1.st.com (10.75.127.16) To SFHDAG5NODE1.st.com (10.75.127.13) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-04-06_08:, , signatures=0 X-MIME-Autoconverted: from 8bit to quoted-printable by mx08-.pphosted.com id w36FF9s8018376 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 91.207.212.93 Subject: [Qemu-devel] [ARM/FDPIC 4/4] linux-user: ARM-FDPIC: Add arm get tls syscall support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Co-Authored-By: Mickaël Guêné Signed-off-by: Christophe Lyon -- 2.6.3 Reviewed-by: Peter Maydell diff --git a/linux-user/arm/target_syscall.h b/linux-user/arm/target_syscall.h index 94e2a42..afc0772 100644 --- a/linux-user/arm/target_syscall.h +++ b/linux-user/arm/target_syscall.h @@ -16,6 +16,7 @@ struct target_pt_regs { #define ARM_NR_breakpoint (ARM_NR_BASE + 1) #define ARM_NR_cacheflush (ARM_NR_BASE + 2) #define ARM_NR_set_tls (ARM_NR_BASE + 5) +#define ARM_NR_get_tls (ARM_NR_BASE + 6) #define ARM_NR_semihosting 0x123456 #define ARM_NR_thumb_semihosting 0xAB diff --git a/linux-user/main.c b/linux-user/main.c index 00810d6..1814578 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -720,6 +720,9 @@ void cpu_loop(CPUARMState *env) case ARM_NR_breakpoint: env->regs[15] -= env->thumb ? 2 : 4; goto excp_debug; + case ARM_NR_get_tls: + env->regs[0] = cpu_get_tls(env); + break; default: gemu_log("qemu: Unsupported ARM syscall: 0x%x\n", n);