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[97.113.169.147]) by smtp.gmail.com with ESMTPSA id k185sm4200212pgk.94.2018.02.28.11.31.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 28 Feb 2018 11:31:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 28 Feb 2018 11:31:15 -0800 Message-Id: <20180228193125.20577-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180228193125.20577-1-richard.henderson@linaro.org> References: <20180228193125.20577-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH v3 06/16] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Alex Bennée Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) -- 2.14.3 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index ae16313eb0..e4d2d548ba 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11987,6 +11987,13 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) case 0x19: /* FMULX */ is_fp = true; break; + case 0x1d: /* SQRDMLAH */ + case 0x1f: /* SQRDMLSH */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_RDM)) { + unallocated_encoding(s); + return; + } + break; default: unallocated_encoding(s); return; @@ -12230,6 +12237,28 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) tcg_op, tcg_idx); } break; + case 0x1d: /* SQRDMLAH */ + read_vec_element_i32(s, tcg_res, rd, pass, + is_scalar ? size : MO_32); + if (size == 1) { + gen_helper_neon_qrdmlah_s16(tcg_res, cpu_env, + tcg_op, tcg_idx, tcg_res); + } else { + gen_helper_neon_qrdmlah_s32(tcg_res, cpu_env, + tcg_op, tcg_idx, tcg_res); + } + break; + case 0x1f: /* SQRDMLSH */ + read_vec_element_i32(s, tcg_res, rd, pass, + is_scalar ? size : MO_32); + if (size == 1) { + gen_helper_neon_qrdmlsh_s16(tcg_res, cpu_env, + tcg_op, tcg_idx, tcg_res); + } else { + gen_helper_neon_qrdmlsh_s32(tcg_res, cpu_env, + tcg_op, tcg_idx, tcg_res); + } + break; default: g_assert_not_reached(); }