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X-Received-From: 2a00:1450:400c:c09::242 Subject: [Qemu-devel] [PATCH v3 03/31] target/arm/cpu.h: update comment for half-precision values X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , richard.henderson@linaro.org, qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + 1 file changed, 1 insertion(+) -- 2.15.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 267a9d7e2f..c2bce23fa5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -168,6 +168,7 @@ typedef struct { * Qn = regs[n].d[1]:regs[n].d[0] * Dn = regs[n].d[0] * Sn = regs[n].d[0] bits 31..0 + * Hn = regs[n].d[0] bits 15..0 for even n, and bits 31..16 for odd n * * This corresponds to the architecturally defined mapping between * the two execution states, and means we do not need to explicitly