From patchwork Sat Feb 17 16:40:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 128670 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1740749ljc; Sat, 17 Feb 2018 08:44:44 -0800 (PST) X-Google-Smtp-Source: AH8x225jtmyl93IdLuWYrkmDmymFP/DkbnK6fXREP6S5ncP/S39cXl8LROO9viMB02brf91hzEdB X-Received: by 10.129.228.73 with SMTP id t9mr7032475ywl.354.1518885883970; Sat, 17 Feb 2018 08:44:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1518885883; cv=none; d=google.com; s=arc-20160816; b=qSd3pnkItEXkppVt88IGnc/oIJo71mwsFK8Aeb5tr9nREmq5SPTLi5zM/zqUxMjGF8 lXt9GVKOJMdK0hdAnwDxSU1PZ94mYXTIE35FxirJwqNYQAjw9vRp6ZkZBcEGOzzFmhn4 mZ4QtbIattJrzwCr0rNZBB6aRbrLuX4FjZnw90c4kYJ5T+DDD1EOicMA323SvYfDzS4W igqwXWX7pooWL+JXCKDQ6ZauWeou3X68+TK6lkhtLjSoSrgN/HJSd90xsIg0A0pLmbOQ GKp//uSJTi+je3wqp3y1eSJbo4MFp3+JyK481LsDxzzda76Uf0IXXM3NV85RGJUOM5uH PSjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=YCnoexIrFCa8uCS7AqNN3zLgKIJLZMCsNRmgssGH/NY=; b=B5Sn1OktuyX+44ijgcNhyQAkI7scbpVTD7OzEtQyRagjRRJ4KUSCPiXRE8o56z9Qpl o60eimYxfXuw1AjJcRmvUIGSYxz/OW96ziWhKcNq+lnoFyizwLgCYrmRezJytS2Idyjp y7vU1673AramOJ1u9UakZrDX93pnU3BnWgaD1jp6hBNlwh4+cQP453FMTk/F+5OvWJM+ 5ybRKDMYQY7ACLiE8UYWjCNFZEJ/kcsOVuWkSA1KvqEg7JQJb6yeSnXv/ITnVJ/ht/1L dHFxhwEDVB9YyQPbQBXQpq2I+lYuLec3SjVshYoTqSBtdx11Fs3EOgXz+53mfLbIdQVD nQPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FCOt11Wc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id w3si1199176ybi.754.2018.02.17.08.44.43 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 17 Feb 2018 08:44:43 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FCOt11Wc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39443 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1en5bP-0007cY-EO for patch@linaro.org; Sat, 17 Feb 2018 11:44:43 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46174) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1en5Xa-0005OO-I2 for qemu-devel@nongnu.org; Sat, 17 Feb 2018 11:40:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1en5XY-0001ji-SD for qemu-devel@nongnu.org; Sat, 17 Feb 2018 11:40:46 -0500 Received: from mail-pl0-x242.google.com ([2607:f8b0:400e:c01::242]:37696) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1en5XY-0001jM-Ju for qemu-devel@nongnu.org; Sat, 17 Feb 2018 11:40:44 -0500 Received: by mail-pl0-x242.google.com with SMTP id ay8so3358073plb.4 for ; Sat, 17 Feb 2018 08:40:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references; bh=YCnoexIrFCa8uCS7AqNN3zLgKIJLZMCsNRmgssGH/NY=; b=FCOt11WcEuJRuB0X3rcJskj+BXXvtM33GipK2rB9DgVN4dzbDauDjxVBdFdaVRSmKr V6caPEUQsZR+qTiVnfZRa9PHEEpjALd12yVHWn6wotz5JypqA9nVNbpGcJTK2Kp5HHd1 OEo0tyAzri732KAzlvpYdQBYy5nWPU3cV6oc0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=YCnoexIrFCa8uCS7AqNN3zLgKIJLZMCsNRmgssGH/NY=; b=d1g/2yIxzqs15ZhBy7cVgxfyGOHsAau4Phwfredwc5Ib4qay2zMu/XlVa6fS/OBvU/ w6Ix7WrzmwgR0X4V+QNDxR8mTsa24CoUsncBC2zpHjMnNmsGbb9CKwmjbN6kdhv4pF4C vITzNrdKDmbHpf2tfKboWzdAKRM0tSJo3npKD0EzrBx9cjhiiHxXnK3bs/yGMq9i/OWr xneGfkWSPSElElJmhMiRcMRWC8DDcC/td3phuKcYOgV3iQkc8J0Q/U/L5MUushhmz2Z9 n3icMIP+nq6TuDnZKM71jOEN2Ybx0czcva1HlXkWZy0IZcIarV+V0U+zpA/yFfg+csAq eunA== X-Gm-Message-State: APf1xPAjUa7kis6ODTBTIreQ8aYb65Q9/rLiVICk+3vRtCSS3mNMLh29 2VSGBwX8+Bz4527ng/0VTMf/Img38YA= X-Received: by 2002:a17:902:3a1:: with SMTP id d30-v6mr6019259pld.409.1518885643084; Sat, 17 Feb 2018 08:40:43 -0800 (PST) Received: from cloudburst.twiddle.net ([50.0.192.64]) by smtp.gmail.com with ESMTPSA id a6sm29152324pfi.99.2018.02.17.08.40.41 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 17 Feb 2018 08:40:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sat, 17 Feb 2018 08:40:36 -0800 Message-Id: <20180217164037.15727-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180217164037.15727-1-richard.henderson@linaro.org> References: <20180217164037.15727-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 1/2] tcg: Fold unspecified opcode test into tcg_can_emit_vec_op X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This releases the callers from having to check themselves, which tidies up the code a bit. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.inc.c | 4 ++++ tcg/i386/tcg-target.inc.c | 4 ++++ tcg/tcg-op-gvec.c | 28 ++++++++++++---------------- 3 files changed, 20 insertions(+), 16 deletions(-) -- 2.14.3 Reviewed-by: Peter Maydell diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index be3192078d..9b0a803d79 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -2217,6 +2217,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { + case 0: + /* Unspecified opcode */ + return 1; + case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_mul_vec: diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index fc05909d1d..45943e540c 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -3064,6 +3064,10 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) { switch (opc) { + case 0: + /* Unspecified opcode. */ + return 1; + case INDEX_op_add_vec: case INDEX_op_sub_vec: case INDEX_op_and_vec: diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index bfe44bba81..29f9cf34b4 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -878,7 +878,7 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, store operation. This is true for aarch64 and x86_64 hosts. */ if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32) - && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) { + && tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece)) { uint32_t some = QEMU_ALIGN_DOWN(oprsz, 32); expand_2_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, g->fniv); if (some == oprsz) { @@ -891,12 +891,11 @@ void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, } if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16) - && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) { + && tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece)) { expand_2_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, g->fniv); } else if (TCG_TARGET_HAS_v64 && !g->prefer_i64 && g->fniv && check_size_impl(oprsz, 8) - && (!g->opc - || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) { + && tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece)) { expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, g->fniv); } else if (g->fni8 && check_size_impl(oprsz, 8)) { expand_2_i64(dofs, aofs, oprsz, g->fni8); @@ -926,7 +925,7 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */ if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32) - && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) { + && tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece)) { uint32_t some = QEMU_ALIGN_DOWN(oprsz, 32); expand_2i_vec(g->vece, dofs, aofs, some, 32, TCG_TYPE_V256, c, g->load_dest, g->fniv); @@ -940,13 +939,12 @@ void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, } if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16) - && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) { + && tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece)) { expand_2i_vec(g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, c, g->load_dest, g->fniv); } else if (TCG_TARGET_HAS_v64 && !g->prefer_i64 && g->fniv && check_size_impl(oprsz, 8) - && (!g->opc - || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) { + && tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece)) { expand_2i_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, c, g->load_dest, g->fniv); } else if (g->fni8 && check_size_impl(oprsz, 8)) { @@ -1063,7 +1061,7 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */ if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32) - && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) { + && tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece)) { uint32_t some = QEMU_ALIGN_DOWN(oprsz, 32); expand_3_vec(g->vece, dofs, aofs, bofs, some, 32, TCG_TYPE_V256, g->load_dest, g->fniv); @@ -1078,13 +1076,12 @@ void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, } if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16) - && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) { + && tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece)) { expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 16, TCG_TYPE_V128, g->load_dest, g->fniv); } else if (TCG_TARGET_HAS_v64 && !g->prefer_i64 && g->fniv && check_size_impl(oprsz, 8) - && (!g->opc - || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) { + && tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece)) { expand_3_vec(g->vece, dofs, aofs, bofs, oprsz, 8, TCG_TYPE_V64, g->load_dest, g->fniv); } else if (g->fni8 && check_size_impl(oprsz, 8)) { @@ -1114,7 +1111,7 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */ if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32) - && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) { + && tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece)) { uint32_t some = QEMU_ALIGN_DOWN(oprsz, 32); expand_4_vec(g->vece, dofs, aofs, bofs, cofs, some, 32, TCG_TYPE_V256, g->fniv); @@ -1130,13 +1127,12 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, } if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16) - && (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) { + && tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece)) { expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, 16, TCG_TYPE_V128, g->fniv); } else if (TCG_TARGET_HAS_v64 && !g->prefer_i64 && g->fniv && check_size_impl(oprsz, 8) - && (!g->opc - || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) { + && tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece)) { expand_4_vec(g->vece, dofs, aofs, bofs, cofs, oprsz, 8, TCG_TYPE_V64, g->fniv); } else if (g->fni8 && check_size_impl(oprsz, 8)) {