From patchwork Mon Jan 22 03:41:41 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 125297 Delivered-To: patch@linaro.org Received: by 10.46.66.141 with SMTP id h13csp944662ljf; Sun, 21 Jan 2018 19:49:32 -0800 (PST) X-Google-Smtp-Source: AH8x225KgKpLAczQ8nF4YE3WxflYy25ITGhe1LTPSIrmK+9AslpfxeMtp23veML27IxzSamO1AlD X-Received: by 10.37.82.9 with SMTP id g9mr5270390ybb.238.1516592972643; Sun, 21 Jan 2018 19:49:32 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1516592972; cv=none; d=google.com; s=arc-20160816; b=DXCQpVtpWYeZ3CKIlnDpap2s6k4liUMgnmIfDa8onXhwaX68t12ee2cSiaonWe+XRP zpbfjAd2VTS+bjuCXiKkIwqmzM0SE2HatdNWa8bceG2ayPBhVrplZBnvlbQQCwpJ6n18 Vq2NK7geGECxNeCKK2ulZNimhshxKpHes1yX5KLsXw/G1oO+Du7cXOy1B0H5Sqw1lv2b J4sg1k80AMphu3SLApEe0WxV+kmC7rb1xpnxkb+ia4WdGZTrO+CW62HBAJeYEaenK7Tm mwe1Gk+mLiQnsCTslbPgI88B7TUIZFPEyGUe41b6EikUCc2devlIgr0aBsPs19KNlAog uuoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=exbg9wf3Jf+eXQueDoelCpDBevuBwgH4hqxIz1Ny4ZY=; b=r9SQhROTlLEC6yO2rtn3xPygLxrVvFBUGoDQWCmAOHnLDW0GIYiM4kgj9wdDgyTM/h FZGbWA0y5P6PZl6TsQZZ3ar0z+sNe9IFIRX5FAL+sODBgBmBN2hUnq53c92pO8T8J4jH CC1Bcro6Sba+TrLb3QuJHVe2a8M751UG7rrXzcFeVx58PkM5OADLNGFdCCrtiUe5TucR LmnVnDOD3d1I8QlOD1f0htff/HQ3h/G3Kfd3YuUMa23JnAcewQsZHoyh0R+cXJOq+DK0 qrWjqTZzxgfw7fglu0XfXC6hmkZFTeiQd/PH/9NuuYvhjUHWS5vH7NF87cRWPOovaxZT j2qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hLpfsavx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b30si529676ybj.50.2018.01.21.19.49.32 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 21 Jan 2018 19:49:32 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=hLpfsavx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:41668 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edT6x-0000t8-V8 for patch@linaro.org; Sun, 21 Jan 2018 22:49:32 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60069) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1edT0C-0005KD-TS for qemu-devel@nongnu.org; Sun, 21 Jan 2018 22:42:40 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1edT0B-00063Z-KW for qemu-devel@nongnu.org; Sun, 21 Jan 2018 22:42:32 -0500 Received: from mail-pg0-x241.google.com ([2607:f8b0:400e:c05::241]:35953) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1edT0B-00063G-DS for qemu-devel@nongnu.org; Sun, 21 Jan 2018 22:42:31 -0500 Received: by mail-pg0-x241.google.com with SMTP id k68so6091639pga.3 for ; Sun, 21 Jan 2018 19:42:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=exbg9wf3Jf+eXQueDoelCpDBevuBwgH4hqxIz1Ny4ZY=; b=hLpfsavxvfRCZcP7SIlhX/3epGVHZrypGcpkVq23oY3Izgkt09WnLu1dY6lmGL6cqk eKFEjj6p0LYcm/14u6yBjWPwfTtiSVEjCycJ/0+I2hjnEEMv/MOIILd9eNqcqpbjvAE7 t0XvuntkSwRowtbfn+8ouVCOP+68xfrmVhNZM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=exbg9wf3Jf+eXQueDoelCpDBevuBwgH4hqxIz1Ny4ZY=; b=R5PFyCXBnc6L4fGIfWsThx0ezzbP549ciA9dhpcJXTiYplcvZAM1nR0E/oKOQJN3En QyAswdXbeRUwScopNHHv5CY6yj3B55ZcxYfKRwRueH0TyLbKGnmDIdDSINXn1IGDB3g1 IFq1+jVYX+t8p8nGoJzN5Pvujigu9nGrrCMGjXnmSmnQQXzsPv4o3YKHs1J3WSI6P6Fs X8f8rKrwoTyqxJRFx4SrFe3zu/JsuTGhkH72rDuJwiCSBATeMNNsWKu+7gwpvcTbIAP5 BLGLx41AoXcq/snZ4h38/G0L2WJspctkNTOeNuQgKHyqSP/7nLqv1mCeABJiJOpxAaJ8 Kz2A== X-Gm-Message-State: AKwxytehqadhhMYU2aiSlW3/gsCObaXYM6VhmFNWCoNilzmhITgyK+QD emCjxOQwLtYYbe9TACy8XQtDEzyHGow= X-Received: by 10.99.126.89 with SMTP id o25mr6079058pgn.161.1516592550048; Sun, 21 Jan 2018 19:42:30 -0800 (PST) Received: from cloudburst.twiddle.net (174-21-6-47.tukw.qwest.net. [174.21.6.47]) by smtp.gmail.com with ESMTPSA id z125sm182023pfz.27.2018.01.21.19.42.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Jan 2018 19:42:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Sun, 21 Jan 2018 19:41:41 -0800 Message-Id: <20180122034217.19593-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180122034217.19593-1-richard.henderson@linaro.org> References: <20180122034217.19593-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::241 Subject: [Qemu-devel] [PULL 07/43] target/hppa: Implement the system mask instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/hppa/helper.h | 4 +++ target/hppa/op_helper.c | 14 ++++++++ target/hppa/translate.c | 96 ++++++++++++++++++++++++++++++++++++++++++++++++- 3 files changed, 113 insertions(+), 1 deletion(-) -- 2.14.3 diff --git a/target/hppa/helper.h b/target/hppa/helper.h index c720de523b..254a4da133 100644 --- a/target/hppa/helper.h +++ b/target/hppa/helper.h @@ -76,3 +76,7 @@ DEF_HELPER_FLAGS_4(fmpyfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpynfadd_s, TCG_CALL_NO_RWG, i32, env, i32, i32, i32) DEF_HELPER_FLAGS_4(fmpyfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) + +#ifndef CONFIG_USER_ONLY +DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tr, env, tr) +#endif diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 479bfc0fdf..1c3e043cc0 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -601,3 +601,17 @@ float64 HELPER(fmpynfadd_d)(CPUHPPAState *env, float64 a, float64 b, float64 c) update_fr0_op(env, GETPC()); return ret; } + +#ifndef CONFIG_USER_ONLY +target_ureg HELPER(swap_system_mask)(CPUHPPAState *env, target_ureg nsm) +{ + target_ulong psw = env->psw; + /* ??? On second reading this condition simply seems + to be undefined rather than a diagnosed trap. */ + if (nsm & ~psw & PSW_Q) { + dynexcp(env, EXCP_ILL, GETPC()); + } + env->psw = (psw & ~PSW_SM) | (nsm & PSW_SM); + return psw & PSW_SM; +} +#endif diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 8a40c3f46b..0c6d7898a2 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -295,6 +295,10 @@ typedef struct DisasContext { updated the iaq for the next instruction to be executed. */ #define DISAS_IAQ_N_STALE DISAS_TARGET_1 +/* Similarly, but we want to return to the main loop immediately + to recognize unmasked interrupts. */ +#define DISAS_IAQ_N_STALE_EXIT DISAS_TARGET_2 + typedef struct DisasInsn { uint32_t insn, mask; DisasJumpType (*trans)(DisasContext *ctx, uint32_t insn, @@ -693,6 +697,14 @@ static DisasJumpType gen_illegal(DisasContext *ctx) return nullify_end(ctx, gen_excp(ctx, EXCP_ILL)); } +#define CHECK_MOST_PRIVILEGED(EXCP) \ + do { \ + if (ctx->privilege != 0) { \ + nullify_over(ctx); \ + return nullify_end(ctx, gen_excp(ctx, EXCP)); \ + } \ + } while (0) + static bool use_goto_tb(DisasContext *ctx, target_ureg dest) { /* Suppress goto_tb in the case of single-steping and IO. */ @@ -1971,6 +1983,79 @@ static DisasJumpType trans_ldsid(DisasContext *ctx, uint32_t insn, return DISAS_NEXT; } +#ifndef CONFIG_USER_ONLY +/* Note that ssm/rsm instructions number PSW_W and PSW_E differently. */ +static target_ureg extract_sm_imm(uint32_t insn) +{ + target_ureg val = extract32(insn, 16, 10); + + if (val & PSW_SM_E) { + val = (val & ~PSW_SM_E) | PSW_E; + } + if (val & PSW_SM_W) { + val = (val & ~PSW_SM_W) | PSW_W; + } + return val; +} + +static DisasJumpType trans_rsm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + target_ureg sm = extract_sm_imm(insn); + TCGv_reg tmp; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + tmp = get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); + tcg_gen_andi_reg(tmp, tmp, ~sm); + gen_helper_swap_system_mask(tmp, cpu_env, tmp); + save_gpr(ctx, rt, tmp); + + /* Exit the TB to recognize new interrupts, e.g. PSW_M. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} + +static DisasJumpType trans_ssm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rt = extract32(insn, 0, 5); + target_ureg sm = extract_sm_imm(insn); + TCGv_reg tmp; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + tmp = get_temp(ctx); + tcg_gen_ld_reg(tmp, cpu_env, offsetof(CPUHPPAState, psw)); + tcg_gen_ori_reg(tmp, tmp, sm); + gen_helper_swap_system_mask(tmp, cpu_env, tmp); + save_gpr(ctx, rt, tmp); + + /* Exit the TB to recognize new interrupts, e.g. PSW_I. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} + +static DisasJumpType trans_mtsm(DisasContext *ctx, uint32_t insn, + const DisasInsn *di) +{ + unsigned rr = extract32(insn, 16, 5); + TCGv_reg tmp, reg; + + CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR); + nullify_over(ctx); + + reg = load_gpr(ctx, rr); + tmp = get_temp(ctx); + gen_helper_swap_system_mask(tmp, cpu_env, reg); + + /* Exit the TB to recognize new interrupts. */ + return nullify_end(ctx, DISAS_IAQ_N_STALE_EXIT); +} +#endif /* !CONFIG_USER_ONLY */ + static const DisasInsn table_system[] = { { 0x00000000u, 0xfc001fe0u, trans_break }, /* We don't implement space register, so MTSP is a nop. */ @@ -1982,6 +2067,11 @@ static const DisasInsn table_system[] = { { 0x000008a0u, 0xfc1fffe0u, trans_mfctl }, { 0x00000400u, 0xffffffffu, trans_sync }, { 0x000010a0u, 0xfc1f3fe0u, trans_ldsid }, +#ifndef CONFIG_USER_ONLY + { 0x00000e60u, 0xfc00ffe0u, trans_rsm }, + { 0x00000d60u, 0xfc00ffe0u, trans_ssm }, + { 0x00001860u, 0xffe0ffffu, trans_mtsm }, +#endif }; static DisasJumpType trans_base_idx_mod(DisasContext *ctx, uint32_t insn, @@ -4100,12 +4190,14 @@ static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + DisasJumpType is_jmp = ctx->base.is_jmp; - switch (ctx->base.is_jmp) { + switch (is_jmp) { case DISAS_NORETURN: break; case DISAS_TOO_MANY: case DISAS_IAQ_N_STALE: + case DISAS_IAQ_N_STALE_EXIT: copy_iaoq_entry(cpu_iaoq_f, ctx->iaoq_f, cpu_iaoq_f); copy_iaoq_entry(cpu_iaoq_b, ctx->iaoq_b, cpu_iaoq_b); nullify_save(ctx); @@ -4113,6 +4205,8 @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) case DISAS_IAQ_N_UPDATED: if (ctx->base.singlestep_enabled) { gen_excp_1(EXCP_DEBUG); + } else if (is_jmp == DISAS_IAQ_N_STALE_EXIT) { + tcg_gen_exit_tb(0); } else { tcg_gen_lookup_and_goto_ptr(); }