From patchwork Fri Dec 29 06:31:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 122914 Delivered-To: patch@linaro.org Received: by 10.140.22.227 with SMTP id 90csp4336730qgn; Thu, 28 Dec 2017 22:52:48 -0800 (PST) X-Google-Smtp-Source: ACJfBosh5ChdT0nZwc5zQJ7UU99lxX8M1T7qViLu+SKEY3OSG4I/FOJJ9lzYwmNTvzKciCm33qPw X-Received: by 10.37.117.5 with SMTP id q5mr7546904ybc.99.1514530368105; Thu, 28 Dec 2017 22:52:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1514530368; cv=none; d=google.com; s=arc-20160816; b=xpcQBhrWmBhkZK5xw+t9SedU899xyESY5bsMxEI55N2Lz/LfKQ9khVc3OMVI/opL78 RkAcmKXGcQ+xHIE0PjKhT5G8TnjQNZjcVSEbket1Q4tjFma18NFinavlopNqtkFC+T6e u+iZCvw4o4gJCogfkn43q9xhBjbkiS0jDKBV209I3aVeOvUGuWCTju7J4Doi0dMiedQl /bnpQN3ZcG2pXwP1fTqVnOu3E0f3n2qbSm7qxAUfbddT2hqyXTh7wok3rF69jBLqZJ1a m3vpxmRJFsygxZ+KVfbQZOpcPpyF1PcW8hN1ztMz5FtCvFKSpYUv2f1bJTd+edojM8oH 5hUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=talmSVHwRXdw03fUreRWnWW4DTYfYqHjhW7delSexI0=; b=rmJHY1KiLF8lIcIGGL99X/Lh3FV5JMP0nxniCSfR5BWr+KqcjO1kI1WWpHNAGEttUL RS2G0t2BPosrCqGr/MR42n9Bm+p2IF1cZYowSRYwSQjj89g5+HVRkwRyw0hFlLJTdnYr XOw4NUJASj7q5pqGyWjYsdbfmjfVmY7JvNk338gZ2IOAr3lrIq+6YJ/qgVBiHYKRwPf7 Q04v/TRYA7WMBcIyxpqxyE7VDGdu1udRUYWRW9P7ZxJiCnI0+nSAGWnsbzBVeSG5wpVl +h20fmFlLwz1U4u+MF12p5TyLDp94PwVgHYlVWkO5xHwIKg77wRCNe8CpYyS7bJC3e5k JGig== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FGDiMFsF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id j15si6576985ywa.386.2017.12.28.22.52.48 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 28 Dec 2017 22:52:48 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FGDiMFsF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:57054 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eUoX9-0003bO-Gw for patch@linaro.org; Fri, 29 Dec 2017 01:52:47 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50933) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1eUoDX-0003Hx-1K for qemu-devel@nongnu.org; Fri, 29 Dec 2017 01:32:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1eUoDV-0004qx-1e for qemu-devel@nongnu.org; Fri, 29 Dec 2017 01:32:30 -0500 Received: from mail-pf0-x243.google.com ([2607:f8b0:400e:c00::243]:47011) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1eUoDU-0004qX-PY for qemu-devel@nongnu.org; Fri, 29 Dec 2017 01:32:28 -0500 Received: by mail-pf0-x243.google.com with SMTP id c204so21819872pfc.13 for ; Thu, 28 Dec 2017 22:32:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=talmSVHwRXdw03fUreRWnWW4DTYfYqHjhW7delSexI0=; b=FGDiMFsFeCLJwvJW6qpwiLuMUPhK9FzYEauTcPF7X+/1lGXMwWRlGWQcNh1DKuJtM9 Si3ASGIGr4zfsft97MfREJpvc7HvkzkT5TN8bM2t+0qh93DyG0pjITzLs88gLfjv/jXS kOELqae6itTdFgdvErjy0GdxGkS7gjz4jn764= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=talmSVHwRXdw03fUreRWnWW4DTYfYqHjhW7delSexI0=; b=qe1J9Let+P5AomdBwWZtJLcWtzXHpbnQvQQh2CPaiT9Hz819++i/hnP4yTmG2ZHrfT Nbw6XtjHlMk9wOea+YosVrPEhEgjBTq3jehVdsFecCbESgKi8ScXQ3zt0RVORRjNgTpM POHdf0ZgsVZ8jqhevGvHlNMLDGKw9ugYJHLMjCkPh4uCzQ3xXcBvjjSxlYBQk6VzD1+W ifk00/60mTB1NGnl/L21vwOzU/z0s6uDjjkw/MQSDyQReW+AyKlFm3z5aqCDrs/juNh7 yUXTdiEVycqubAreh/W09y1IGBpC0INxrudiE3KdUr1MoBkqVYgHC+q1ACqc8qLhV2yg z/Yw== X-Gm-Message-State: AKGB3mImc2r8jPv0FsNxFoVqTAj8e7ZMHGfBArAd2isNcRYrAPEhhjLv ODtXqG/EQNkN1345ZTttPgzXQLFb5Qw= X-Received: by 10.101.99.139 with SMTP id h11mr11067098pgv.141.1514529147465; Thu, 28 Dec 2017 22:32:27 -0800 (PST) Received: from cloudburst.twiddle.net (97-113-183-164.tukw.qwest.net. [97.113.183.164]) by smtp.gmail.com with ESMTPSA id c28sm76539063pfe.69.2017.12.28.22.32.26 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 28 Dec 2017 22:32:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 28 Dec 2017 22:31:37 -0800 Message-Id: <20171229063145.29167-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171229063145.29167-1-richard.henderson@linaro.org> References: <20171229063145.29167-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::243 Subject: [Qemu-devel] [PATCH 30/38] target/hppa: Optimize for flat addressing space X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: deller@gmx.de Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Linux sets sr4-sr7 all to the same value, which means that we need not do any runtime computation to find out what space to use in forming the GVA. Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 8 +++++++- target/hppa/translate.c | 32 +++++++++++++++++++++----------- 2 files changed, 28 insertions(+), 12 deletions(-) -- 2.14.3 diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index c072f55d31..8c8ce66094 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -282,11 +282,12 @@ static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, return hppa_form_gva_psw(env->psw, spc, off); } -/* Since PSW_V and PSW_CB will never need to be in tb->flags, reuse them. +/* Since PSW_{V,I,CB} will never need to be in tb->flags, reuse them. * TB_FLAG_NONSEQ indicates that the two instructions in the insn queue * are non-sequential. */ #define TB_FLAG_NONSEQ PSW_V +#define TB_FLAG_SR_SAME PSW_I #define TB_FLAG_PRIV_SHIFT 8 static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, @@ -294,6 +295,7 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, uint32_t *pflags) { bool nonseq = env->iaoq_b != env->iaoq_f + 4; + bool sr_same = false; int priv; /* TB lookup assumes that PC contains the complete virtual address. @@ -316,12 +318,16 @@ static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, *pc = env->iaoq_f & -4; *cs_base = 0; } + sr_same = (env->sr[4] == env->sr[5]) + & (env->sr[4] == env->sr[6]) + & (env->sr[4] == env->sr[7]); #endif /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ *pflags = (env->psw & (PSW_W | PSW_C | PSW_D)) | env->psw_n * PSW_N | nonseq * TB_FLAG_NONSEQ + | sr_same * TB_FLAG_SR_SAME | (priv << TB_FLAG_PRIV_SHIFT); } diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 68f0b86c72..23ec43eff8 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -280,6 +280,7 @@ typedef struct DisasContext { TCGLabel *null_lab; uint32_t insn; + uint32_t tb_flags; int mmu_idx; int privilege; bool psw_n_nonzero; @@ -320,6 +321,7 @@ typedef struct DisasInsn { /* global register indexes */ static TCGv_reg cpu_gr[32]; static TCGv_i64 cpu_sr[4]; +static TCGv_i64 cpu_srH; static TCGv_reg cpu_iaoq_f; static TCGv_reg cpu_iaoq_b; static TCGv_i64 cpu_iasq_f; @@ -357,8 +359,8 @@ void hppa_translate_init(void) "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }; /* SR[4-7] are not global registers so that we can index them. */ - static const char sr_names[4][4] = { - "sr0", "sr1", "sr2", "sr3" + static const char sr_names[5][4] = { + "sr0", "sr1", "sr2", "sr3", "srH" }; int i; @@ -374,6 +376,9 @@ void hppa_translate_init(void) offsetof(CPUHPPAState, sr[i]), sr_names[i]); } + cpu_srH = tcg_global_mem_new_i64(cpu_env, + offsetof(CPUHPPAState, sr[4]), + sr_names[4]); for (i = 0; i < ARRAY_SIZE(vars); ++i) { const GlobalVar *v = &vars[i]; @@ -601,6 +606,8 @@ static void load_spr(DisasContext *ctx, TCGv_i64 dest, unsigned reg) #else if (reg < 4) { tcg_gen_mov_i64(dest, cpu_sr[reg]); + } else if (ctx->tb_flags & TB_FLAG_SR_SAME) { + tcg_gen_mov_i64(dest, cpu_srH); } else { tcg_gen_ld_i64(dest, cpu_env, offsetof(CPUHPPAState, sr[reg])); } @@ -1353,6 +1360,9 @@ static TCGv_i64 space_select(DisasContext *ctx, int sp, TCGv_reg base) load_spr(ctx, spc, sp); return spc; } + if (ctx->tb_flags & TB_FLAG_SR_SAME) { + return cpu_srH; + } ptr = tcg_temp_new_ptr(); tmp = tcg_temp_new(); @@ -1396,7 +1406,7 @@ static void form_gva(DisasContext *ctx, TCGv_tl *pgva, TCGv_reg *pofs, #else TCGv_tl addr = get_temp_tl(ctx); tcg_gen_extu_reg_tl(addr, modify <= 0 ? ofs : base); - if (ctx->base.tb->flags & PSW_W) { + if (ctx->tb_flags & PSW_W) { tcg_gen_andi_tl(addr, addr, 0x3fffffffffffffffull); } if (!is_phys) { @@ -2103,6 +2113,7 @@ static DisasJumpType trans_mtsp(DisasContext *ctx, uint32_t insn, if (rs >= 4) { tcg_gen_st_i64(t64, cpu_env, offsetof(CPUHPPAState, sr[rs])); + ctx->tb_flags &= ~TB_FLAG_SR_SAME; } else { tcg_gen_mov_i64(cpu_sr[rs], t64); } @@ -2394,7 +2405,7 @@ static DisasJumpType trans_ixtlbx(DisasContext *ctx, uint32_t insn, /* Exit TB for ITLB change if mmu is enabled. This *should* not be the case, since the OS TLB fill handler runs with mmu disabled. */ - return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + return nullify_end(ctx, !is_data && (ctx->tb_flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } @@ -2430,7 +2441,7 @@ static DisasJumpType trans_pxtlbx(DisasContext *ctx, uint32_t insn, } /* Exit TB for TLB change if mmu is enabled. */ - return nullify_end(ctx, !is_data && (ctx->base.tb->flags & PSW_C) + return nullify_end(ctx, !is_data && (ctx->tb_flags & PSW_C) ? DISAS_IAQ_N_STALE : DISAS_NEXT); } @@ -4546,15 +4557,14 @@ static int hppa_tr_init_disas_context(DisasContextBase *dcbase, ctx->mmu_idx = MMU_USER_IDX; ctx->iaoq_f = ctx->base.pc_first; #else - ctx->privilege = (ctx->base.tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; - ctx->mmu_idx = (ctx->base.tb->flags & PSW_D - ? ctx->privilege : MMU_PHYS_IDX); + ctx->tb_flags = ctx->base.tb->flags; + ctx->privilege = (ctx->tb_flags >> TB_FLAG_PRIV_SHIFT) & 3; + ctx->mmu_idx = (ctx->tb_flags & PSW_D ? ctx->privilege : MMU_PHYS_IDX); /* Recover the IAOQ value from the GVA + PRIV. */ ctx->iaoq_f = (ctx->base.pc_first & ~ctx->base.tb->cs_base) + ctx->privilege; #endif - ctx->iaoq_b = (ctx->base.tb->flags & TB_FLAG_NONSEQ - ? -1 : ctx->iaoq_f + 4); + ctx->iaoq_b = (ctx->tb_flags & TB_FLAG_NONSEQ ? -1 : ctx->iaoq_f + 4); ctx->iaoq_n = -1; ctx->iaoq_n_var = NULL; @@ -4578,7 +4588,7 @@ static void hppa_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) /* Seed the nullification status from PSW[N], as saved in TB->FLAGS. */ ctx->null_cond = cond_make_f(); ctx->psw_n_nonzero = false; - if (ctx->base.tb->flags & PSW_N) { + if (ctx->tb_flags & PSW_N) { ctx->null_cond.c = TCG_COND_ALWAYS; ctx->psw_n_nonzero = true; }