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[174.21.7.63]) by smtp.gmail.com with ESMTPSA id t84sm26209657pfe.160.2017.12.18.09.46.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Dec 2017 09:46:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 18 Dec 2017 09:45:45 -0800 Message-Id: <20171218174552.18871-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20171218174552.18871-1-richard.henderson@linaro.org> References: <20171218174552.18871-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::243 Subject: [Qemu-devel] [PATCH 16/23] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 30 ++++++++++++++++++++++++++++++ target/arm/sve.def | 13 +++++++++++++ 2 files changed, 43 insertions(+) -- 2.14.3 diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 83793ab169..7edec8ba96 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -127,6 +127,36 @@ static void do_zzz_genfn(DisasContext *s, arg_rrr_esz *a, GVecGen3Fn *fn) do_genfn3(s, fn, a->esz, a->rd, a->rn, a->rm); } +void trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_add); +} + +void trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_sub); +} + +void trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_ssadd); +} + +void trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_sssub); +} + +void trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_usadd); +} + +void trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) +{ + do_zzz_genfn(s, a, tcg_gen_gvec_ussub); +} + void trans_AND_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn) { do_zzz_genfn(s, a, tcg_gen_gvec_and); diff --git a/target/arm/sve.def b/target/arm/sve.def index 3ae871394c..a33fec4f33 100644 --- a/target/arm/sve.def +++ b/target/arm/sve.def @@ -53,6 +53,9 @@ # Named instruction formats. These are generally used to # reduce the amount of duplication between instruction patterns. +# Three operand +@rd_rn_rm_esz ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz + # Three operand with unused vector element size @rd_rn_rm ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0 @@ -183,6 +186,16 @@ MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm_esz MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm_esz # MAD MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm_esz # MSB +### SVE Integer Arithmetic - Unpredicated Group + +# SVE integer add/subtract vectors (unpredicated) +ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm_esz +SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm_esz +SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm_esz +UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm_esz +SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm_esz +UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm_esz + ### SVE Logical - Unpredicated Group # SVE bitwise logical operations (unpredicated)