| Message ID | 20171218171758.16964-5-richard.henderson@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tcg: generic vector operations | expand |
On 12/18/2017 02:17 PM, Richard Henderson wrote: > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/arm/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 96316700dd..3ff4dea6b8 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -492,7 +492,7 @@ typedef struct CPUARMState { > * the two execution states, and means we do not need to explicitly > * map these registers when changing states. > */ > - float64 regs[64]; > + float64 regs[64] QEMU_ALIGNED(16); > > uint32_t xregs[16]; > /* We store these fpcsr fields separately for convenience. */ >
diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 96316700dd..3ff4dea6b8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -492,7 +492,7 @@ typedef struct CPUARMState { * the two execution states, and means we do not need to explicitly * map these registers when changing states. */ - float64 regs[64]; + float64 regs[64] QEMU_ALIGNED(16); uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */