From patchwork Tue Oct 31 14:54:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 117634 Delivered-To: patch@linaro.org Received: by 10.80.245.45 with SMTP id t42csp4049501edm; Tue, 31 Oct 2017 07:55:36 -0700 (PDT) X-Google-Smtp-Source: ABhQp+Sb94zNirB8dygDs8RzowPQ+faj2h5HbGxRVhQrvPoObWgbynr4EFO7mWERdLp5sbNxIquy X-Received: by 10.13.192.196 with SMTP id b187mr1443108ywd.416.1509461736092; Tue, 31 Oct 2017 07:55:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509461736; cv=none; d=google.com; s=arc-20160816; b=Nv93mSSS+8IPkzAP2q4D6/8wwwBOb5LHyrFnrgjZ7gkl6r+gaJt5uXS1YZDIaWsoPW N/1XAs3AhcQFkUD54R6yqstLgpzfLSviz67a0oGjNYz712J5dITLLkYUYajkcIEsDqFr sOp3GxgKPte64NqGG45XNn3WHwkqjgH+Q5hhhAbdasCXvS10qKfEiMU6jZWLtyseYs8H h0fgAUhKewU6tYDka/+Oh94hAN/s8H1VP3Ed4tFXwIHgMutfKfuEFPE3qOUra78tLNMq fhbt9j0Wj5otP7ChILI5v7MiWu0hv+jKwBgCTZ/PEiDD33brJBYOgK+kg+WluGkyNiSE n4YQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=J4tcVroP/ZB/1X/CBfYacbnGKmiMPBQP6TkCK0zQugg=; b=SIJ1jK4fdUPldLcuDo7G+KuXa4IZROBQN8r9fExTQ1i3XpTlh3i66kFnMg1Wbo/sTE uoNfe1+rn6x47cHQ35bE+EoV9bsXsCvaSXV/Mdyq14lyieucWKztMgLK8AP/5o5+FOY2 suYbT9GfLYXh1h36HauU2Z50A3Z/3u3vrLtMjjZmY9n0MetaBuUe9enQoOm6hwcWnaJa nRzctZt9qWDOUorV+8FhVfIvzTgguTCFBIjGT6rd8NpRvNs985vZu9itf46G3o95dRN8 3QcOvNgpJR+u4Zj8y8bP0h/Ddw789HZt5dXWh5NPjy5O3G8h+O36GTrJu481YxhHm8K8 Hsmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FcBl/0C4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id j125si435669ywg.68.2017.10.31.07.55.35 for (version=TLS1 cipher=AES128-SHA bits=128/128); Tue, 31 Oct 2017 07:55:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=FcBl/0C4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:45992 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9Xx1-0000iZ-Am for patch@linaro.org; Tue, 31 Oct 2017 10:55:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59371) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1e9Xwb-0000cG-6L for qemu-devel@nongnu.org; Tue, 31 Oct 2017 10:55:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1e9XwW-000721-PN for qemu-devel@nongnu.org; Tue, 31 Oct 2017 10:55:09 -0400 Received: from mail-wr0-x241.google.com ([2a00:1450:400c:c0c::241]:49654) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1e9XwW-00071g-FE for qemu-devel@nongnu.org; Tue, 31 Oct 2017 10:55:04 -0400 Received: by mail-wr0-x241.google.com with SMTP id g90so16207337wrd.6 for ; Tue, 31 Oct 2017 07:55:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J4tcVroP/ZB/1X/CBfYacbnGKmiMPBQP6TkCK0zQugg=; b=FcBl/0C49ZaeRq2dhXv07FA18XADCDEiCPJnlOLwCcXlcY+jJ9azsNKVe26l1pi1DC EiE5oHc9bHn0OpR7O9SxFThMSiaP75PcnPeXbYDfMPiX4qmZ0hZq3F/wLiy6WdFaZ+bK B7lTUZqDVy+T1WQuqmxkIUb0S71+76aLCnAnA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J4tcVroP/ZB/1X/CBfYacbnGKmiMPBQP6TkCK0zQugg=; b=e8nGNMZBnc7GmXSrZ0wvFtyNzuo7NzahmMFo5qeqLKy+1zFjlrmgwmxoiQJNA6nRhL aIWByxOAoQRGH7Yx08N8HGMmSINClZuTBMJ0eCY/lfX9EVAyUCDf59wIaR0YKhKngMLv pSIKKZuz628QX8m31HCW4z2FST8qL8wU3cFoEgaqJ7IsiuS5jQmCJB0riFLaXS0k7fhn Ebcn94pFc0/DF3E0Yg/c+mRBvnjUf2bG/ljRpkI/dnigD9NCb+YirDvITNOxmZU6qUEy Lk85nwhGWO/EPRScxBjrAWwbKI+YqPxyKd8GynCI04Qx8Mpfrx/KD1NnNdgG/ZgCqGZM 2diw== X-Gm-Message-State: AMCzsaWoQW1qjj9kDfabk5XzAhTV1wAxkg7+PBqwQD9DcdesXr7Cs0l9 Jk3x1LKNzIOnZK7vf+uD52jNDO5DHqM= X-Received: by 10.223.190.132 with SMTP id i4mr2289577wrh.123.1509461703013; Tue, 31 Oct 2017 07:55:03 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id m64sm980644wmb.10.2017.10.31.07.54.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 31 Oct 2017 07:54:58 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id BF2B23E0D6D; Tue, 31 Oct 2017 14:54:57 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Tue, 31 Oct 2017 14:54:40 +0000 Message-Id: <20171031145444.13766-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171031145444.13766-1-alex.bennee@linaro.org> References: <20171031145444.13766-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:400c:c0c::241 Subject: [Qemu-devel] [RISU PATCH 3/7] aarch64.risu: remove duplicate AdvSIMD scalar 2 reg misc block X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While at that also sort alphabetically and nicely align for eye-balling the patterns. Signed-off-by: Alex Bennée --- aarch64.risu | 110 +++++++++++++++++++---------------------------------------- 1 file changed, 35 insertions(+), 75 deletions(-) -- 2.14.2 diff --git a/aarch64.risu b/aarch64.risu index c9f24cd..f3e588b 100644 --- a/aarch64.risu +++ b/aarch64.risu @@ -2166,85 +2166,45 @@ FACGT A64_V 01 1 11110 1 size:1 1 rm:5 11101 1 rn:5 rd:5 \ !constraints { $size != 11; } -# C3.6.12 AdvSIMD scalar 2reg misc -CMGTzero A64_V 01 0 11110 size:2 10000 01000 10 rn:5 rd:5 -CMGEzero A64_V 01 1 11110 size:2 10000 01000 10 rn:5 rd:5 -CMEQzero A64_V 01 0 11110 size:2 10000 01001 10 rn:5 rd:5 -CMLEzero A64_V 01 1 11110 size:2 10000 01001 10 rn:5 rd:5 -CMLTzero A64_V 01 0 11110 size:2 10000 01010 10 rn:5 rd:5 -ABS A64_V 01 0 11110 size:2 10000 01011 10 rn:5 rd:5 -NEG A64_V 01 1 11110 size:2 10000 01011 10 rn:5 rd:5 - -FCMGT_S2MISC A64_V 01 0 11110 size:2 10000 01100 10 rn:5 rd:5 -FCMEQ_S2MISC A64_V 01 0 11110 size:2 10000 01101 10 rn:5 rd:5 -FCMLT_S2MISC A64_V 01 0 11110 size:2 10000 01110 10 rn:5 rd:5 -FCMGE_S2MISC A64_V 01 1 11110 size:2 10000 01100 10 rn:5 rd:5 -FCMLE_S2MISC A64_V 01 1 11110 size:2 10000 01101 10 rn:5 rd:5 - -SCVTF_S2MISC A64_V 01 0 11110 0 sz 10000 11101 10 rn:5 rd:5 -UCVTF_S2MISC A64_V 01 1 11110 0 sz 10000 11101 10 rn:5 rd:5 - -FCVTNS_S2MISC A64_V 01 0 11110 0 sz 10000 11010 10 rn:5 rd:5 -FCVTMS_S2MISC A64_V 01 0 11110 0 sz 10000 11011 10 rn:5 rd:5 -FCVTAS_S2MISC A64_V 01 0 11110 0 sz 10000 11100 10 rn:5 rd:5 -FCVTPS_S2MISC A64_V 01 0 11110 1 sz 10000 11010 10 rn:5 rd:5 -FCVTZS_S2MISC A64_V 01 0 11110 1 sz 10000 11011 10 rn:5 rd:5 - -FCVTNU_S2MISC A64_V 01 1 11110 0 sz 10000 11010 10 rn:5 rd:5 -FCVTMU_S2MISC A64_V 01 1 11110 0 sz 10000 11011 10 rn:5 rd:5 -FCVTAU_S2MISC A64_V 01 1 11110 0 sz 10000 11100 10 rn:5 rd:5 -FCVTPU_S2MISC A64_V 01 1 11110 1 sz 10000 11010 10 rn:5 rd:5 -FCVTZU_S2MISC A64_V 01 1 11110 1 sz 10000 11011 10 rn:5 rd:5 - -FCVTXN_S2MISC A64_V 01 1 11110 0 sz 10000 10110 10 rn:5 rd:5 - -SUQADD_S2MISC A64_V 01 0 11110 size:2 10000 00011 10 rn:5 rd:5 -USQADD_S2MISC A64_V 01 1 11110 size:2 10000 00011 10 rn:5 rd:5 -SQABS_S2MISC A64_V 01 0 11110 size:2 10000 00111 10 rn:5 rd:5 -SQNEG_S2MISC A64_V 01 1 11110 size:2 10000 00111 10 rn:5 rd:5 - -# XXX lots of others in this group - # C3.6.12 AdvSIMD scalar two-reg misc # 31 30 29 28 27 26 25 24 23 22 21 20 16 12 11 10 9 5 4 0 # 0 1 U 1 1 1 1 0 size 1 0 0 0 0 [ opcode ] 1 0 [ Rn ] [ Rd ] # U size opcode -SUQADDs A64_V 01 0 11110 size:2 10000 00011 10 rn:5 rd:5 -SQABSs A64_V 01 0 11110 size:2 10000 00111 10 rn:5 rd:5 -CMGTzs A64_V 01 0 11110 size:2 10000 01000 10 rn:5 rd:5 -CMEQzs A64_V 01 0 11110 size:2 10000 01001 10 rn:5 rd:5 -CMLTzs A64_V 01 0 11110 size:2 10000 01010 10 rn:5 rd:5 -ABSs A64_V 01 0 11110 size:2 10000 01011 10 rn:5 rd:5 -SQXTN_SQXTN2s A64_V 01 0 11110 size:2 10000 10100 10 rn:5 rd:5 -FCVTNSvs A64_V 01 0 11110 0 size:1 10000 11010 10 rn:5 rd:5 -FCVTMSvs A64_V 01 0 11110 0 size:1 10000 11011 10 rn:5 rd:5 -FCVTASvs A64_V 01 0 11110 0 size:1 10000 11100 10 rn:5 rd:5 -SCVTFvis A64_V 01 0 11110 0 size:1 10000 11101 10 rn:5 rd:5 -FCMGTzs A64_V 01 0 11110 1 size:1 10000 01100 10 rn:5 rd:5 -FCMEQzs A64_V 01 0 11110 1 size:1 10000 01101 10 rn:5 rd:5 -FCMLTzs A64_V 01 0 11110 1 size:1 10000 01110 10 rn:5 rd:5 -FCVTPSvs A64_V 01 0 11110 1 size:1 10000 11010 10 rn:5 rd:5 -FCVTZSvis A64_V 01 0 11110 1 size:1 10000 11011 10 rn:5 rd:5 -FRECPEs A64_V 01 0 11110 1 size:1 10000 11101 10 rn:5 rd:5 -FRECPX A64_V 01 0 11110 1 size:1 10000 11111 10 rn:5 rd:5 -USQADDs A64_V 01 1 11110 size:2 10000 00011 10 rn:5 rd:5 -SQNEGs A64_V 01 1 11110 size:2 10000 00111 10 rn:5 rd:5 -CMGzs A64_V 01 1 11110 size:2 10000 01000 10 rn:5 rd:5 -CMLEzs A64_V 01 1 11110 size:2 10000 01001 10 rn:5 rd:5 -NEGvs A64_V 01 1 11110 size:2 10000 01011 10 rn:5 rd:5 -SQXTUN_SQXTUN2s A64_V 01 1 11110 size:2 10000 10010 10 rn:5 rd:5 -UQXTN_UQXTN2s A64_V 01 1 11110 size:2 10000 10100 10 rn:5 rd:5 -FCVTXN_FCVTXN2s A64_V 01 1 11110 0 size:1 10000 10110 10 rn:5 rd:5 -FCVTNUvs A64_V 01 1 11110 0 size:1 10000 11010 10 rn:5 rd:5 -FCVTMUvs A64_V 01 1 11110 0 size:1 10000 11011 10 rn:5 rd:5 -FCVTAUvs A64_V 01 1 11110 0 size:1 10000 11100 10 rn:5 rd:5 -UCVTFvis A64_V 01 1 11110 0 size:1 10000 11101 10 rn:5 rd:5 -FCMGEzs A64_V 01 1 11110 1 size:1 10000 01100 10 rn:5 rd:5 -FCMLEzs A64_V 01 1 11110 1 size:1 10000 01101 10 rn:5 rd:5 -FCVTPUvs A64_V 01 1 11110 1 size:1 10000 11010 10 rn:5 rd:5 -FCVTZUvis A64_V 01 1 11110 1 size:1 10000 11011 10 rn:5 rd:5 -FRSQRTEs A64_V 01 1 11110 1 size:1 10000 11101 10 rn:5 rd:5 - +ABSs A64_V 01 0 11110 size:2 10000 01011 10 rn:5 rd:5 +CMEQzs A64_V 01 0 11110 size:2 10000 01001 10 rn:5 rd:5 +CMGTzs A64_V 01 0 11110 size:2 10000 01000 10 rn:5 rd:5 +CMGzs A64_V 01 1 11110 size:2 10000 01000 10 rn:5 rd:5 +CMLEzs A64_V 01 1 11110 size:2 10000 01001 10 rn:5 rd:5 +CMLTzs A64_V 01 0 11110 size:2 10000 01010 10 rn:5 rd:5 +FCMEQzs A64_V 01 0 11110 1 size:1 10000 01101 10 rn:5 rd:5 +FCMGEzs A64_V 01 1 11110 1 size:1 10000 01100 10 rn:5 rd:5 +FCMGTzs A64_V 01 0 11110 1 size:1 10000 01100 10 rn:5 rd:5 +FCMLEzs A64_V 01 1 11110 1 size:1 10000 01101 10 rn:5 rd:5 +FCMLTzs A64_V 01 0 11110 1 size:1 10000 01110 10 rn:5 rd:5 +FCVTASvs A64_V 01 0 11110 0 size:1 10000 11100 10 rn:5 rd:5 +FCVTAUvs A64_V 01 1 11110 0 size:1 10000 11100 10 rn:5 rd:5 +FCVTMSvs A64_V 01 0 11110 0 size:1 10000 11011 10 rn:5 rd:5 +FCVTMUvs A64_V 01 1 11110 0 size:1 10000 11011 10 rn:5 rd:5 +FCVTNSvs A64_V 01 0 11110 0 size:1 10000 11010 10 rn:5 rd:5 +FCVTNUvs A64_V 01 1 11110 0 size:1 10000 11010 10 rn:5 rd:5 +FCVTPSvs A64_V 01 0 11110 1 size:1 10000 11010 10 rn:5 rd:5 +FCVTPUvs A64_V 01 1 11110 1 size:1 10000 11010 10 rn:5 rd:5 +FCVTXN_FCVTXN2s A64_V 01 1 11110 0 size:1 10000 10110 10 rn:5 rd:5 +FCVTZSvis A64_V 01 0 11110 1 size:1 10000 11011 10 rn:5 rd:5 +FCVTZUvis A64_V 01 1 11110 1 size:1 10000 11011 10 rn:5 rd:5 +FRECPEs A64_V 01 0 11110 1 size:1 10000 11101 10 rn:5 rd:5 +FRECPX A64_V 01 0 11110 1 size:1 10000 11111 10 rn:5 rd:5 +FRSQRTEs A64_V 01 1 11110 1 size:1 10000 11101 10 rn:5 rd:5 +NEGvs A64_V 01 1 11110 size:2 10000 01011 10 rn:5 rd:5 +SCVTFvis A64_V 01 0 11110 0 size:1 10000 11101 10 rn:5 rd:5 +SQABSs A64_V 01 0 11110 size:2 10000 00111 10 rn:5 rd:5 +SQNEGs A64_V 01 1 11110 size:2 10000 00111 10 rn:5 rd:5 +SQXTN_SQXTN2s A64_V 01 0 11110 size:2 10000 10100 10 rn:5 rd:5 +SQXTUN_SQXTUN2s A64_V 01 1 11110 size:2 10000 10010 10 rn:5 rd:5 +SUQADDs A64_V 01 0 11110 size:2 10000 00011 10 rn:5 rd:5 +UCVTFvis A64_V 01 1 11110 0 size:1 10000 11101 10 rn:5 rd:5 +UQXTN_UQXTN2s A64_V 01 1 11110 size:2 10000 10100 10 rn:5 rd:5 +USQADDs A64_V 01 1 11110 size:2 10000 00011 10 rn:5 rd:5 # C3.6.13 AdvSIMD scalar x indexed element # Complete coverage.