From patchwork Thu Sep 7 22:40:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111974 Delivered-To: patch@linaro.org Received: by 10.140.94.239 with SMTP id g102csp721825qge; Thu, 7 Sep 2017 15:43:32 -0700 (PDT) X-Received: by 10.55.23.205 with SMTP id 74mr1243281qkx.134.1504824212751; Thu, 07 Sep 2017 15:43:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504824212; cv=none; d=google.com; s=arc-20160816; b=nB6liYB7xWtnJIaDQb+ZIK2BqM0LneN7nCDzlSSQofOc0hbinI0rndzbBn/hFCAxmn +YZIsrBKLASSNNCkB9rhBxafvh16gCKc1+vwJe4UComgi97M49P8cN/PqGG9MSTjP/dU ZFBtgPSyNUuUh1c0DeQ2D4ci+rxXxB/srtw9EDrBr6FqT5TibWeKkt1Vf12BCvOMrbzW VLlOVz3Axexm9saOllMNCa+qv/v1qltEBOui1YkQdvG7Vxwr2l7Pzqpq379QdloPEa0Q w2a/1ScJul2r2GEOSLpr78a3B5+/moIqg7dKs+1ghTtf0MyJ9q6X5JiMaL2GZmYuIH7Z xMEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=AsoJlWiUc2xIlOEw/Aqp10soH/fjgwUnxjIzF/rW2gY=; b=WjvnCJR/PDGAHMTLCHuer528ky6o5kWa/yyqc+WAH9nz5b5Oz0oLF2iBplmGmtnXHi no/jjGs7nFNzc2QWS+1RARuEZ+Vny5MJv8eNttOHowqjYHG6DWB/c1E68DQc4NosEXQ7 c0eoUDUXeqMsAHe0Sulg0RQFgE9a3ZEPBmlQYyfO7VJ0pJURon0CPNzy90TLGTBbelER tvrytfEDqMwVFGZGU/ZsHPRlJ0cLrcws7n1znQNGEkRbqA3xZfdcSnEItZgfqIOcoxza UuzhOsWeLXJ2T7k3zQAtSioigd/egUH4xQyclb8o9ngN0LOvg6nKJlCz06CHXPGfduBp zRqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MilTOnt5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f1si465372qtl.107.2017.09.07.15.43.32 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 07 Sep 2017 15:43:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=MilTOnt5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42521 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq5WE-0004c8-JB for patch@linaro.org; Thu, 07 Sep 2017 18:43:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52010) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq5Tv-0002yJ-PS for qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dq5Tq-000859-RW for qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:07 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:33213) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dq5Tq-00084W-J7 for qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:02 -0400 Received: by mail-pg0-x22a.google.com with SMTP id t3so1832996pgt.0 for ; Thu, 07 Sep 2017 15:41:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=AsoJlWiUc2xIlOEw/Aqp10soH/fjgwUnxjIzF/rW2gY=; b=MilTOnt5bR0VOkATf0S31FOyrhcAg563hoBcomNSz7fPMeVCo632x9OfhF1sKsHtHK hOLpjeS6Y83B9BUvVefe7eR3/hoKTIa1QR8GY3uRSMYQHoQFmP1exzeEwByagYLIvZ8E xLvdKUbCzUR+tYyrDc/cZHf1EsZ/HgFjqsfvU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=AsoJlWiUc2xIlOEw/Aqp10soH/fjgwUnxjIzF/rW2gY=; b=dmRuSurYUcXHYVDHzqrPuciStcnpeL+rr6kyveY7dQJhuy1uzaL6D3doTKTiUJkT4g 6hMmKqZ1DxveqLNjuUpuGORGeudxc0vXDO6el2zYix+EiMcMgQoO4G/pl740BF83yaaK 4uOp0MGIZh6HK051aFBetUwtJIV00FSkgEGBD+SUVniJ281PIMA32otvmkS6ullu6RSL XrstGZtfeOAO5hV4iFhYEmZNqb6n3hdOyN1Ok2QNa1Fmw542uTcd09/Gnylq04c1XBCe 7uNYj4FhD5uYkbeu50J9Swzen88SP3FaGO2bEJ7EBUyNE7Q2lAgpaQo3FAQi1SrZ21+A AkWg== X-Gm-Message-State: AHPjjUjiRJzIIov4ozjTUNJO2NVMLMi2mi0wQ0uNRfeP9JqeBex5EPH9 hiT9KvlUV+tFn5RCSx5o+A== X-Google-Smtp-Source: ADKCNb5aCksKsO78EiindBGqssFd6nR9200pM+/zUiK0wZshWGqYnBqNQZchTfjYW4X7tdcdb8MapA== X-Received: by 10.99.98.131 with SMTP id w125mr977385pgb.214.1504824061249; Thu, 07 Sep 2017 15:41:01 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id h19sm770678pfh.142.2017.09.07.15.41.00 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 15:41:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 15:40:33 -0700 Message-Id: <20170907224051.21518-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907224051.21518-1-richard.henderson@linaro.org> References: <20170907224051.21518-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PULL 05/23] tcg/s390: Introduce TCG_REG_TB X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.h | 2 +- tcg/s390/tcg-target.inc.c | 71 +++++++++++++++++++++++++++++++++++++++-------- 2 files changed, 61 insertions(+), 12 deletions(-) -- 2.13.5 diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 52010c30cb..9c9c8cd464 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -95,7 +95,7 @@ extern uint64_t s390_facilities; #define TCG_TARGET_HAS_extrl_i64_i32 0 #define TCG_TARGET_HAS_extrh_i64_i32 0 #define TCG_TARGET_HAS_goto_ptr 1 -#define TCG_TARGET_HAS_direct_jump 1 +#define TCG_TARGET_HAS_direct_jump (s390_facilities & FACILITY_GEN_INST_EXT) #define TCG_TARGET_HAS_div2_i64 1 #define TCG_TARGET_HAS_rot_i64 1 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index ee0dff995a..e007586315 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -51,6 +51,12 @@ /* A scratch register that may be be used throughout the backend. */ #define TCG_TMP0 TCG_REG_R1 +/* A scratch register that holds a pointer to the beginning of the TB. + We don't need this when we have pc-relative loads with the general + instructions extension facility. */ +#define TCG_REG_TB TCG_REG_R12 +#define USE_REG_TB (!(s390_facilities & FACILITY_GEN_INST_EXT)) + #ifndef CONFIG_SOFTMMU #define TCG_GUEST_BASE_REG TCG_REG_R13 #endif @@ -556,8 +562,8 @@ static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) } /* load a register with an immediate value */ -static void tcg_out_movi(TCGContext *s, TCGType type, - TCGReg ret, tcg_target_long sval) +static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, + tcg_target_long sval, bool in_prologue) { static const S390Opcode lli_insns[4] = { RI_LLILL, RI_LLILH, RI_LLIHL, RI_LLIHH @@ -601,13 +607,22 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } - /* Try for PC-relative address load. */ + /* Try for PC-relative address load. For odd addresses, + attempt to use an offset from the start of the TB. */ if ((sval & 1) == 0) { ptrdiff_t off = tcg_pcrel_diff(s, (void *)sval) >> 1; if (off == (int32_t)off) { tcg_out_insn(s, RIL, LARL, ret, off); return; } + } else if (USE_REG_TB && !in_prologue) { + ptrdiff_t off = sval - (uintptr_t)s->code_gen_ptr; + if (off == sextract64(off, 0, 20)) { + /* This is certain to be an address within TB, and therefore + OFF will be negative; don't try RX_LA. */ + tcg_out_insn(s, RXY, LAY, ret, TCG_REG_TB, TCG_REG_NONE, off); + return; + } } /* If extended immediates are not present, then we may have to issue @@ -663,6 +678,11 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } +static void tcg_out_movi(TCGContext *s, TCGType type, + TCGReg ret, tcg_target_long sval) +{ + tcg_out_movi_int(s, type, ret, sval, false); +} /* Emit a load/store type instruction. Inputs are: DATA: The register to be loaded or stored. @@ -739,6 +759,13 @@ static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, void *abs) return; } } + if (USE_REG_TB) { + ptrdiff_t disp = abs - (void *)s->code_gen_ptr; + if (disp == sextract64(disp, 0, 20)) { + tcg_out_ld(s, type, dest, TCG_REG_TB, disp); + return; + } + } tcg_out_movi(s, TCG_TYPE_PTR, dest, addr & ~0xffff); tcg_out_ld(s, type, dest, dest, addr & 0xffff); @@ -1690,6 +1717,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_goto_tb: + a0 = args[0]; if (s->tb_jmp_insn_offset) { /* branch displacement must be aligned for atomic patching; * see if we need to add extra nop before branch @@ -1697,21 +1725,34 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, if (!QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) { tcg_out16(s, NOP); } + tcg_debug_assert(!USE_REG_TB); tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4)); - s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s); + s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); s->code_ptr += 2; } else { - /* load address stored at s->tb_jmp_target_addr + args[0] */ - tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_TMP0, - s->tb_jmp_target_addr + args[0]); + /* load address stored at s->tb_jmp_target_addr + a0 */ + tcg_out_ld_abs(s, TCG_TYPE_PTR, TCG_REG_TB, + s->tb_jmp_target_addr + a0); /* and go there */ - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_TMP0); + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, TCG_REG_TB); + } + s->tb_jmp_reset_offset[a0] = tcg_current_code_size(s); + + /* For the unlinked path of goto_tb, we need to reset + TCG_REG_TB to the beginning of this TB. */ + if (USE_REG_TB) { + int ofs = -tcg_current_code_size(s); + assert(ofs == (int16_t)ofs); + tcg_out_insn(s, RI, AGHI, TCG_REG_TB, ofs); } - s->tb_jmp_reset_offset[args[0]] = tcg_current_code_size(s); break; case INDEX_op_goto_ptr: - tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, args[0]); + a0 = args[0]; + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); + } + tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, a0); break; OP_32_64(ld8u): @@ -2476,6 +2517,9 @@ static void tcg_target_init(TCGContext *s) /* XXX many insns can't be used with R0, so we better avoid it for now */ tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); + if (USE_REG_TB) { + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); + } } #define FRAME_SIZE ((int)(TCG_TARGET_CALL_STACK_OFFSET \ @@ -2496,12 +2540,17 @@ static void tcg_target_qemu_prologue(TCGContext *s) #ifndef CONFIG_SOFTMMU if (guest_base >= 0x80000) { - tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); } #endif tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + if (USE_REG_TB) { + tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, + tcg_target_call_iarg_regs[1]); + } + /* br %r3 (go to TB) */ tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]);