From patchwork Thu Sep 7 22:40:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111984 Delivered-To: patch@linaro.org Received: by 10.37.128.210 with SMTP id c18csp763257ybm; Thu, 7 Sep 2017 15:50:54 -0700 (PDT) X-Received: by 10.237.63.82 with SMTP id q18mr1454145qtf.274.1504824654112; Thu, 07 Sep 2017 15:50:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504824654; cv=none; d=google.com; s=arc-20160816; b=rvP0v+vDydPkRERfEZOy1PRmqFZvM4cZpVMfaYI1OwUHDaIP7cjlEtfY9R0sNX4nkL pV3nd6xUdzq7C9dzm1u7wZvNneIWl8M6HVzOftWfWKh6PhnndXNDZA3XsrPdaQWDKv+D fhfrRoWCQCLPKNVn47pT887t0lvn83NBSBZXZueT5GXlrPdsONhX7C8yAoSrXMt1CPYL ev+7AiqtkHkjn50TM+ytVbyQTxnmKCt9OBNJEBlxoHswIEDo7wcaZ8oJus6REtO+nAY0 qNxnP4WivZWOA/zpvP6i5c0t9xOaEgXTXjt8CxhX6i2GKIG7dFFX7NdyCjkZtVbco+P7 i+xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=GyID29fvgFconnX4hc2+M1A5fpECok1c1ASb0Yls7AI=; b=unyRxoBk7sYV60Wm0b7xMUch36GcQytP5vu+Tl7eM7YBpU9Bqivv1HggWlqDtqci/X RZyC2SU4Oy5DDsG4dU9xczDuHLBiPI1RPYN95mcYuR8IMP1RTaCpraEP6rgvPzRB5K6q gvEzq+4unP53lELa/0HtWZX4LEHI9oHO+U/vq+ol0m6q5c6HpPKeMx6jyseh2Qt9QDKD 6ro/WQnYFfgkseyJwzSMcbqx+Sldyo0wv35wkyCdiqbzLhiDVOGqvtAXdInr3IAy3yKW xy7Ze8NL99lGLVU6HWyfH0Ijsu6HxU68SPnPnoeyNHpeWpQ0zNoFSPa6Zi/Nq+bpwj4R ARwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=c+eSWtgp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id d18si521638qte.200.2017.09.07.15.50.53 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 07 Sep 2017 15:50:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=c+eSWtgp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42552 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq5dL-0002V9-SP for patch@linaro.org; Thu, 07 Sep 2017 18:50:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52194) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq5U6-00038Q-EK for qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dq5U1-0008Fv-Ea for qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:18 -0400 Received: from mail-pg0-x229.google.com ([2607:f8b0:400e:c05::229]:34449) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dq5U1-0008FE-8L for qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:13 -0400 Received: by mail-pg0-x229.google.com with SMTP id q68so1823968pgq.1 for ; Thu, 07 Sep 2017 15:41:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GyID29fvgFconnX4hc2+M1A5fpECok1c1ASb0Yls7AI=; b=c+eSWtgplQVb6y3VMQpZFHgivuI4nvnIPHf5QqNy3vA7mu4nxgpHE0pl4m2OBXOgkV qwDDgCiNKlugaHpyKbo0u3ckP7r7wRnIo3aIfLWctzJuqfhjC2WmTwQNiVHgeqh2Ea9l j3eVaBXjbtbg8J64tpXxzDtdMx5MeXsqVl1KI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GyID29fvgFconnX4hc2+M1A5fpECok1c1ASb0Yls7AI=; b=oc2b/Yt/xkohOl/yDyT24fozPYzC9cLfyj8pT+EYf4iyet5sKq6l8KoyN1aUr8qqwq F0M7+peShrWKC9MnK5jpP4pBjaTlFTnhRJgdnVVJU3RrUGE7kHhcKaFc8ViAFEh7eRl0 VCauHU/7FKIwBLV+tdgN0GS8q3FZjFqIWqjGIIKfOngQm/uo06h/jyNelZbQ3vhucJ85 W13YsRuP+e2451wrsIwKcxyeT7yDZfylrOLFMzowT6RyEvue0Fy3sanh8UZtqiQiXose xlOEhuv8uLbpUmTP00tn/Kf2mxicZstXvqBY91xbRXYrSvoWxiK/yT0MnSIJ2xd60B2n 6/Ag== X-Gm-Message-State: AHPjjUjiUG/BHyj5hF/AU2F7J0DSQC41w/RMw2fU1wYIhboliG+5rGfC zPX3i0htCo9UIZBjjCHEjA== X-Google-Smtp-Source: ADKCNb5RiOrZUxD6zNRfOR586hfFn8TuLhutQEKM4FlS1Zfl3w91fJT3WtNB9laBGV5BIOs39QXpYA== X-Received: by 10.99.171.73 with SMTP id k9mr962353pgp.196.1504824071887; Thu, 07 Sep 2017 15:41:11 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id h19sm770678pfh.142.2017.09.07.15.41.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 15:41:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 15:40:40 -0700 Message-Id: <20170907224051.21518-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907224051.21518-1-richard.henderson@linaro.org> References: <20170907224051.21518-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::229 Subject: [Qemu-devel] [PULL 12/23] tcg/aarch64: Use constant pool for movi X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 1 + tcg/aarch64/tcg-target.inc.c | 62 +++++++++++++++++++++++--------------------- 2 files changed, 33 insertions(+), 30 deletions(-) -- 2.13.5 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 1bdbd7058b..c2525066ab 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -125,5 +125,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); #ifdef CONFIG_SOFTMMU #define TCG_TARGET_NEED_LDST_LABELS #endif +#define TCG_TARGET_NEED_POOL_LABELS #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index c7c751bafc..c2f3812214 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -10,6 +10,7 @@ * See the COPYING file in the top-level directory for details. */ +#include "tcg-pool.inc.c" #include "qemu/bitops.h" /* We're going to re-use TCGType in setting of the SF bit, which controls @@ -587,9 +588,11 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext, static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_target_long value) { - int i, wantinv, shift; tcg_target_long svalue = value; tcg_target_long ivalue = ~value; + tcg_target_long t0, t1, t2; + int s0, s1; + AArch64Insn opc; /* For 32-bit values, discard potential garbage in value. For 64-bit values within [2**31, 2**32-1], we can create smaller sequences by @@ -638,38 +641,29 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, } } - /* Would it take fewer insns to begin with MOVN? For the value and its - inverse, count the number of 16-bit lanes that are 0. */ - for (i = wantinv = 0; i < 64; i += 16) { - tcg_target_long mask = 0xffffull << i; - wantinv -= ((value & mask) == 0); - wantinv += ((ivalue & mask) == 0); - } - - if (wantinv <= 0) { - /* Find the lowest lane that is not 0x0000. */ - shift = ctz64(value) & (63 & -16); - tcg_out_insn(s, 3405, MOVZ, type, rd, value >> shift, shift); - /* Clear out the lane that we just set. */ - value &= ~(0xffffUL << shift); - /* Iterate until all non-zero lanes have been processed. */ - while (value) { - shift = ctz64(value) & (63 & -16); - tcg_out_insn(s, 3405, MOVK, type, rd, value >> shift, shift); - value &= ~(0xffffUL << shift); - } + /* Would it take fewer insns to begin with MOVN? */ + if (ctpop64(value) >= 32) { + t0 = ivalue; + opc = I3405_MOVN; } else { - /* Like above, but with the inverted value and MOVN to start. */ - shift = ctz64(ivalue) & (63 & -16); - tcg_out_insn(s, 3405, MOVN, type, rd, ivalue >> shift, shift); - ivalue &= ~(0xffffUL << shift); - while (ivalue) { - shift = ctz64(ivalue) & (63 & -16); - /* Provide MOVK with the non-inverted value. */ - tcg_out_insn(s, 3405, MOVK, type, rd, ~(ivalue >> shift), shift); - ivalue &= ~(0xffffUL << shift); + t0 = value; + opc = I3405_MOVZ; + } + s0 = ctz64(t0) & (63 & -16); + t1 = t0 & ~(0xffffUL << s0); + s1 = ctz64(t1) & (63 & -16); + t2 = t1 & ~(0xffffUL << s1); + if (t2 == 0) { + tcg_out_insn_3405(s, opc, type, rd, t0 >> s0, s0); + if (t1 != 0) { + tcg_out_insn(s, 3405, MOVK, type, rd, value >> s1, s1); } + return; } + + /* For more than 2 insns, dump it into the constant pool. */ + new_pool_label(s, value, R_AARCH64_CONDBR19, s->code_ptr, 0); + tcg_out_insn(s, 3305, LDR, 0, rd); } /* Define something more legible for general use. */ @@ -2030,6 +2024,14 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_insn(s, 3207, RET, TCG_REG_LR); } +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i = 0; i < count; ++i) { + p[i] = NOP; + } +} + typedef struct { DebugFrameHeader h; uint8_t fde_def_cfa[4];