From patchwork Thu Sep 7 22:40:37 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111988 Delivered-To: patch@linaro.org Received: by 10.37.128.210 with SMTP id c18csp765922ybm; Thu, 7 Sep 2017 15:54:08 -0700 (PDT) X-Received: by 10.200.57.83 with SMTP id t19mr1479036qtb.150.1504824847940; Thu, 07 Sep 2017 15:54:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504824847; cv=none; d=google.com; s=arc-20160816; b=ScfYvzMjXLVq4XhIDXd+y4ITG62nrM5XbImwDiGKBdO5S+J7augW3mzTW+rCJxGEqE XRSMf/6E22xtlQV66OWo1fOTezsQWgLGEiEa/GryPIf6z6kq+7LVIkyxczFEBaMFLHc9 HssVJIEQXadusm0Q1/2wkTcsp9bayjhUL/I5iOndzmBe7lcu+0HNq7+Afu5FWwo9z4gm nedKMmbqqVhFJxhdMjxRX3dq1EcKKhvnp1GwZMenUn05gg53mxqyE5IXJDuisVI99TUj ZECCQbX2EgNKs9IYjFff1MCRRW4r7GHk3YP/dIBLQXUdfUnAdp1fUFTtlVzbXV4EHEXt IO9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=6BZlkqXrN46LW44YziE4XJkyjG2E07rBsSu0/OqDgZ4=; b=hNSTocrbNe2x8jyoJW0kVW/g1W4+3TtgHAorYAKz1e35zFSH+RNbf6qQaspu0r3Y/8 oufd0G1u3guCy++qwLy2dY7838GSl3KBuVuS2cM0neVCClRGqiDTrhVyhNxAQdtk5Ckc wMZ6hp4Q/inKa7U3nd9wm36NZJqhESyu2xq4CWDfCr2u+SQVNoEE4Xfyb3AWEEJhjKzs xdktpnM+b3qpXLPyxrSZEk4HUZ1mQ4X+5Rs93LyoX4Etvnz1ssbbm32BxC4Lx4bYbNHA XpiBsSaAkMlxBNz66E4EAr6oHodStTX+MhBNTRI+2fu9sCb1p1YFell3oKIo1pO7SA14 CPWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X0C8TEZH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id s53si495332qtj.322.2017.09.07.15.54.07 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 07 Sep 2017 15:54:07 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X0C8TEZH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:42563 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq5gT-0005IS-MR for patch@linaro.org; Thu, 07 Sep 2017 18:54:05 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52125) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dq5U2-00034f-10 for qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dq5Tw-0008AU-UJ for qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:14 -0400 Received: from mail-pg0-x236.google.com ([2607:f8b0:400e:c05::236]:36680) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dq5Tw-00089a-Mf for qemu-devel@nongnu.org; Thu, 07 Sep 2017 18:41:08 -0400 Received: by mail-pg0-x236.google.com with SMTP id m9so1818296pgd.3 for ; Thu, 07 Sep 2017 15:41:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6BZlkqXrN46LW44YziE4XJkyjG2E07rBsSu0/OqDgZ4=; b=X0C8TEZHwGE0r3KhVzHXhj0eogm0P9cokFHCW8TqzmLZTf9NXsf2q2fujsOy0aK2Em v06iN67Et+Fl1YkwiHOHvcc6GZESsgj8rwUBAb/yGk+pnzroRAq3GiVyVKg/wX6JBJue gTwn4nKGZhL3UHuHTK1arPonfB1wbFm2MVQ+A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6BZlkqXrN46LW44YziE4XJkyjG2E07rBsSu0/OqDgZ4=; b=cBOCBeYTBh4kZTU1mbf9323lrfa1fpHDbZKO5nt5VfVrPBJGLA6gtkdo1sfQVFdc/1 M0IN/J8q8Vzpq4P5F0p8CgU7LFOOvT5P7S9BfF3oczYjq/xAegmgxUeM467hHfLhCKnh vkmQFjggAgETSFmdUP6zKPBhp/yR0hwxb66xmRzfjRCbdRPGoMUb2vyr1fhZMjXqUq1y jkMyUrAblF2bhvSm7q1ZBDmCkfF0Ej36T8MnhbM3HvRHK/CJePMLuBlVKA1Y5rt123zC wTE1L7gZMAT529b34nafJqH4Q8DBwh/9gHn1RPmQj0uWK4d9AGi9LOE63K1n1+U0QG4K 3GEQ== X-Gm-Message-State: AHPjjUiAj/W+fVAvaxDd2OgM591kDBj0aXSAv2SX/3eShFkPEV5WE2LA +gclL6wxRGTcm6L81+UCnQ== X-Google-Smtp-Source: ADKCNb69USj5KoA5Uhw6McWLOPHNZowhGXze5T7tUwEnLZx9RftruzBpr6yYUoin0GBZB/xYAXPDsw== X-Received: by 10.99.3.9 with SMTP id 9mr932146pgd.205.1504824067239; Thu, 07 Sep 2017 15:41:07 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id h19sm770678pfh.142.2017.09.07.15.41.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 07 Sep 2017 15:41:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Thu, 7 Sep 2017 15:40:37 -0700 Message-Id: <20170907224051.21518-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170907224051.21518-1-richard.henderson@linaro.org> References: <20170907224051.21518-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::236 Subject: [Qemu-devel] [PULL 09/23] tcg/s390: Use constant pool for ori X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 74 ++++++++++++++++++++++------------------------- 1 file changed, 34 insertions(+), 40 deletions(-) -- 2.13.5 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 4be57c5765..83fac71c31 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -225,6 +225,7 @@ typedef enum S390Opcode { RXY_LRVH = 0xe31f, RXY_LY = 0xe358, RXY_NG = 0xe380, + RXY_OG = 0xe381, RXY_STCY = 0xe372, RXY_STG = 0xe324, RXY_STHY = 0xe370, @@ -1004,55 +1005,60 @@ static void tgen_andi(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) } } -static void tgen64_ori(TCGContext *s, TCGReg dest, tcg_target_ulong val) +static void tgen_ori(TCGContext *s, TCGType type, TCGReg dest, uint64_t val) { static const S390Opcode oi_insns[4] = { RI_OILL, RI_OILH, RI_OIHL, RI_OIHH }; - static const S390Opcode nif_insns[2] = { + static const S390Opcode oif_insns[2] = { RIL_OILF, RIL_OIHF }; int i; /* Look for no-op. */ - if (val == 0) { + if (unlikely(val == 0)) { return; } - if (s390_facilities & FACILITY_EXT_IMM) { - /* Try all 32-bit insns that can perform it in one go. */ - for (i = 0; i < 4; i++) { - tcg_target_ulong mask = (0xffffull << i*16); - if ((val & mask) != 0 && (val & ~mask) == 0) { - tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16); - return; - } + /* Try all 32-bit insns that can perform it in one go. */ + for (i = 0; i < 4; i++) { + tcg_target_ulong mask = (0xffffull << i*16); + if ((val & mask) != 0 && (val & ~mask) == 0) { + tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16); + return; } + } - /* Try all 48-bit insns that can perform it in one go. */ + /* Try all 48-bit insns that can perform it in one go. */ + if (s390_facilities & FACILITY_EXT_IMM) { for (i = 0; i < 2; i++) { tcg_target_ulong mask = (0xffffffffull << i*32); if ((val & mask) != 0 && (val & ~mask) == 0) { - tcg_out_insn_RIL(s, nif_insns[i], dest, val >> i*32); + tcg_out_insn_RIL(s, oif_insns[i], dest, val >> i*32); return; } } + } + /* Use the constant pool if USE_REG_TB, but not for small constants. */ + if (maybe_out_small_movi(s, type, TCG_TMP0, val)) { + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RR, OR, dest, TCG_TMP0); + } else { + tcg_out_insn(s, RRE, OGR, dest, TCG_TMP0); + } + } else if (USE_REG_TB) { + tcg_out_insn(s, RXY, OG, dest, TCG_REG_TB, TCG_REG_NONE, 0); + new_pool_label(s, val, R_390_20, s->code_ptr - 2, + -(intptr_t)s->code_gen_ptr); + } else { /* Perform the OR via sequential modifications to the high and low parts. Do this via recursion to handle 16-bit vs 32-bit masks in each half. */ - tgen64_ori(s, dest, val & 0x00000000ffffffffull); - tgen64_ori(s, dest, val & 0xffffffff00000000ull); - } else { - /* With no extended-immediate facility, we don't need to be so - clever. Just iterate over the insns and mask in the constant. */ - for (i = 0; i < 4; i++) { - tcg_target_ulong mask = (0xffffull << i*16); - if ((val & mask) != 0) { - tcg_out_insn_RI(s, oi_insns[i], dest, val >> i*16); - } - } + tcg_debug_assert(s390_facilities & FACILITY_EXT_IMM); + tgen_ori(s, type, dest, val & 0x00000000ffffffffull); + tgen_ori(s, type, dest, val & 0xffffffff00000000ull); } } @@ -1872,7 +1878,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, a0 = args[0], a1 = args[1], a2 = (uint32_t)args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I32, a0, a1); - tgen64_ori(s, a0, a2); + tgen_ori(s, TCG_TYPE_I32, a0, a2); } else if (a0 == a1) { tcg_out_insn(s, RR, OR, a0, a2); } else { @@ -2104,7 +2110,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, a0 = args[0], a1 = args[1], a2 = args[2]; if (const_args[2]) { tcg_out_mov(s, TCG_TYPE_I64, a0, a1); - tgen64_ori(s, a0, a2); + tgen_ori(s, TCG_TYPE_I64, a0, a2); } else if (a0 == a1) { tcg_out_insn(s, RRE, OGR, a0, a2); } else { @@ -2312,7 +2318,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; static const TCGTargetOpDef r_0_rI = { .args_ct_str = { "r", "0", "rI" } }; static const TCGTargetOpDef r_0_rJ = { .args_ct_str = { "r", "0", "rJ" } }; - static const TCGTargetOpDef r_0_rN = { .args_ct_str = { "r", "0", "rN" } }; static const TCGTargetOpDef r_0_rM = { .args_ct_str = { "r", "0", "rM" } }; static const TCGTargetOpDef a2_r = { .args_ct_str = { "r", "r", "0", "1", "r", "r" } }; @@ -2353,6 +2358,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_sub_i64: case INDEX_op_and_i32: case INDEX_op_and_i64: + case INDEX_op_or_i32: + case INDEX_op_or_i64: return (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri); case INDEX_op_mul_i32: @@ -2363,19 +2370,6 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) case INDEX_op_mul_i64: return (s390_facilities & FACILITY_GEN_INST_EXT ? &r_0_rJ : &r_0_rI); - case INDEX_op_or_i32: - /* The use of [iNM] constraints are optimization only, since a full - 64-bit immediate OR can always be performed with 4 sequential - OI[LH][LH] instructions. By rejecting certain negative ranges, - the immediate load plus the reg-reg OR is smaller. */ - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_ri : &r_0_ri) - : &r_0_rN); - case INDEX_op_or_i64: - return (s390_facilities & FACILITY_EXT_IMM - ? (s390_facilities & FACILITY_DISTINCT_OPS ? &r_r_rM : &r_0_rM) - : &r_0_rN); - case INDEX_op_xor_i32: /* Without EXT_IMM, no immediates are supported. Otherwise, rejecting certain negative ranges leads to smaller code. */