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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:59 -0700 Message-Id: <20170906160612.22769-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::229 Subject: [Qemu-devel] [PULL 19/32] target/arm: [tcg] Port to insn_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002388959.22386.12439646324427589940.stgit@frigg.lan> Signed-off-by: Richard Henderson --- target/arm/translate.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.c b/target/arm/translate.c index 3138a23e0c..005157225c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11936,6 +11936,16 @@ static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) } } +static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + dc->insn_start_idx = tcg_op_buf_count(); + tcg_gen_insn_start(dc->pc, + (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), + 0); +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11979,10 +11989,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) do { dc->base.num_insns++; - dc->insn_start_idx = tcg_op_buf_count(); - tcg_gen_insn_start(dc->pc, - (dc->condexec_cond << 4) | (dc->condexec_mask >> 1), - 0); + arm_tr_insn_start(&dc->base, cs); if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) { CPUBreakpoint *bp;