From patchwork Wed Sep 6 16:05:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111821 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1134307qge; Wed, 6 Sep 2017 09:19:49 -0700 (PDT) X-Received: by 10.55.156.79 with SMTP id f76mr4354595qke.298.1504714789729; Wed, 06 Sep 2017 09:19:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504714789; cv=none; d=google.com; s=arc-20160816; b=nKrJAMRj70aGm91O1vRsT6xm/Fd45SIxNIOgSkbBob58cevhcjwQd1yBYMNiqkI7+M mJfaBQhd2pHAxuMvUp1dgHdfEf8M5CssfW+YmnA00BqNw4dxRkUt3EfInSZu3EohWF56 WKwSvTugfMzs0yuDoj33i6Yq/e8XIPMYJT4gK/rRDUGzlZk3VwXCV21zwAfHRKDpjaEF 6TeZ+LHWWfEmmp8mJrPbYzyU4oc4+GPJWojeR6XOG6eWRwZ9mzPVHYsZpiUSjEANBSeX BBnukzlz1rFJGTxV4yPxCqQ58pBnuWxY54sQg7u2/MhNLP4e3594IWyVpvfuPydDbtLu hENQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=RBpPMCfof5ruZ/5aJuF/nc5V26lehfTdsSHm+aLUbHg=; b=Ap02a//rQDNtoJeaJF7zxSEP1VPiAxCJGsn6Qu2iaEK0Ah7BnI5HGkplaaMXR1KiPA nRNEL/vOy67visvkaOK3v6BtJs5iAv8w2mrTp/5eSKXzpLLopWXNkuxep6UPWHDgrlKB dnOk3ckzABBPolqzeQLYLHd7VDBiIRCgpo4KI7A9cZWkqvBf68cstZneCftEuhHWMXSh swUutVWDPSMI57HrIkA8699lpe2tlbLyMb2CzBxpUzAkXjMwZVeilps0nNfBzoT0InTk RXZhm+SZzXwLEd1TbjDuejhn/Otrl4TDO6h4GMCeOE4kRFjEiFyuKksZLNlEs0CCih7d DHEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kWQ1BaLl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id r200si221548qke.224.2017.09.06.09.19.49 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 06 Sep 2017 09:19:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kWQ1BaLl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:37008 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpd3L-0002WS-2F for patch@linaro.org; Wed, 06 Sep 2017 12:19:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41776) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpcqf-0000DA-UX for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpcqe-0002T5-LT for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:41 -0400 Received: from mail-pg0-x235.google.com ([2607:f8b0:400e:c05::235]:38905) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpcqe-0002Ss-Ck for qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:40 -0400 Received: by mail-pg0-x235.google.com with SMTP id v66so15891614pgb.5 for ; Wed, 06 Sep 2017 09:06:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RBpPMCfof5ruZ/5aJuF/nc5V26lehfTdsSHm+aLUbHg=; b=kWQ1BaLlERsbz7Ey1Y9RJALRZYvkSSw/YWk/PdOLQq4BeP9iw9AxLJ3A7om0Cz/aMz htYwoK20j8eNrXJVH8zMP0WRc61/pyc5dZy8JwWcHRBnnBIIjHxXkwOvblB5UzltHHE+ kQnD5rXGRoTtmRw05iOSuch36gEAgDSPjnBrE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RBpPMCfof5ruZ/5aJuF/nc5V26lehfTdsSHm+aLUbHg=; b=qnSQ6ZLd/0GC4wN2RUy5KaiTwXnqy0c7A5nZm9IGJU+S5yfTRccnW4btKTUkbjytQe weWsohKNd4gzcN5QyakfJIXnA5STS1krj9EY+Vnxru11VLo0uQxDXJ0NCAMzSR9aAy+p zbtGt3cAmFC6W1M5wWo+95oONxIxuka3GKUZqQruEODt7tFRyKhZIDe89Ypyd71ng8Xx JO3/c4OD6x37I3dnbKx/n1u1YSHfx6m0fyN1qmfE1l70VMHBTti/ubHkdeZ/gEl8csXL PgBBJnARscHB4zcN6Q+R0iKP+kQEeeLVRyRX1anr2ffKBvpcNpuPMLDyHaPi0aMNTVNh NYew== X-Gm-Message-State: AHPjjUhv8u6oVK7kYC1TvOTjsE5/3abGC98SYP6xbOQesOu4N+pQDToc p26kiuEQ+UvgVWBOHGUrGA== X-Google-Smtp-Source: ADKCNb7EdBDftqeTlNT6qU2yshBr6Fod5ttKsPvQ9S9nFhBAA+Md7WRw8mdEWiULxVO1X2xzvfIQoQ== X-Received: by 10.84.130.42 with SMTP id 39mr9090288plc.239.1504713999160; Wed, 06 Sep 2017 09:06:39 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:05:58 -0700 Message-Id: <20170906160612.22769-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::235 Subject: [Qemu-devel] [PULL 18/32] target/arm: [tcg] Port to tb_start X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, =?utf-8?q?Llu=C3=ADs_Vilanova?= , Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Lluís Vilanova Incrementally paves the way towards using the generic instruction translation loop. Signed-off-by: Lluís Vilanova Reviewed-by: Richard Henderson Reviewed-by: Alex Benneé Message-Id: <150002364681.22386.1701754996184325808.stgit@frigg.lan> [rth: Adjust for tb_start interface change.] Signed-off-by: Richard Henderson --- target/arm/translate.c | 82 +++++++++++++++++++++++++++----------------------- 1 file changed, 44 insertions(+), 38 deletions(-) -- 2.13.5 diff --git a/target/arm/translate.c b/target/arm/translate.c index a95c183cee..3138a23e0c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11893,6 +11893,49 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase, return max_insns; } +static void arm_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *dc = container_of(dcbase, DisasContext, base); + + /* A note on handling of the condexec (IT) bits: + * + * We want to avoid the overhead of having to write the updated condexec + * bits back to the CPUARMState for every instruction in an IT block. So: + * (1) if the condexec bits are not already zero then we write + * zero back into the CPUARMState now. This avoids complications trying + * to do it at the end of the block. (For example if we don't do this + * it's hard to identify whether we can safely skip writing condexec + * at the end of the TB, which we definitely want to do for the case + * where a TB doesn't do anything with the IT state at all.) + * (2) if we are going to leave the TB then we call gen_set_condexec() + * which will write the correct value into CPUARMState if zero is wrong. + * This is done both for leaving the TB at the end, and for leaving + * it because of an exception we know will happen, which is done in + * gen_exception_insn(). The latter is necessary because we need to + * leave the TB with the PC/IT state just prior to execution of the + * instruction which caused the exception. + * (3) if we leave the TB unexpectedly (eg a data abort on a load) + * then the CPUARMState will be wrong and we need to reset it. + * This is handled in the same way as restoration of the + * PC in these situations; we save the value of the condexec bits + * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() + * then uses this to restore them after an exception. + * + * Note that there are no instructions which can read the condexec + * bits, and none which can write non-static values to them, so + * we don't need to care about whether CPUARMState is correct in the + * middle of a TB. + */ + + /* Reset the conditional execution bits immediately. This avoids + complications trying to do it at the end of the block. */ + if (dc->condexec_mask || dc->condexec_cond) { + TCGv_i32 tmp = tcg_temp_new_i32(); + tcg_gen_movi_i32(tmp, 0); + store_cpu_field(tmp, condexec_bits); + } +} + /* generate intermediate code for basic block 'tb'. */ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) { @@ -11932,45 +11975,8 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) gen_tb_start(tb); tcg_clear_temp_count(); + arm_tr_tb_start(&dc->base, cs); - /* A note on handling of the condexec (IT) bits: - * - * We want to avoid the overhead of having to write the updated condexec - * bits back to the CPUARMState for every instruction in an IT block. So: - * (1) if the condexec bits are not already zero then we write - * zero back into the CPUARMState now. This avoids complications trying - * to do it at the end of the block. (For example if we don't do this - * it's hard to identify whether we can safely skip writing condexec - * at the end of the TB, which we definitely want to do for the case - * where a TB doesn't do anything with the IT state at all.) - * (2) if we are going to leave the TB then we call gen_set_condexec() - * which will write the correct value into CPUARMState if zero is wrong. - * This is done both for leaving the TB at the end, and for leaving - * it because of an exception we know will happen, which is done in - * gen_exception_insn(). The latter is necessary because we need to - * leave the TB with the PC/IT state just prior to execution of the - * instruction which caused the exception. - * (3) if we leave the TB unexpectedly (eg a data abort on a load) - * then the CPUARMState will be wrong and we need to reset it. - * This is handled in the same way as restoration of the - * PC in these situations; we save the value of the condexec bits - * for each PC via tcg_gen_insn_start(), and restore_state_to_opc() - * then uses this to restore them after an exception. - * - * Note that there are no instructions which can read the condexec - * bits, and none which can write non-static values to them, so - * we don't need to care about whether CPUARMState is correct in the - * middle of a TB. - */ - - /* Reset the conditional execution bits immediately. This avoids - complications trying to do it at the end of the block. */ - if (dc->condexec_mask || dc->condexec_cond) - { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_movi_i32(tmp, 0); - store_cpu_field(tmp, condexec_bits); - } do { dc->base.num_insns++; dc->insn_start_idx = tcg_op_buf_count();