From patchwork Wed Sep 6 14:49:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111792 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp1003667qge; Wed, 6 Sep 2017 07:58:18 -0700 (PDT) X-Received: by 10.55.18.137 with SMTP id 9mr3987685qks.208.1504709898711; Wed, 06 Sep 2017 07:58:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504709898; cv=none; d=google.com; s=arc-20160816; b=vI8a/dBM49T6AUu07Zw9sMDbc4vjcwckIb1CfrNTesZu4pKmsLraNR0EkKl9/1KMqm tDMzqkUjdIQyrErSXeClbbV9SKD8+8aqdGZFHefK+hH7LNAyKbubBPAtltsuZncRvv5A Zf4OMT1bMacW6d82S+xMbymeIn+zYbNIwr611/AjhFNuiae6wQoJMT8ojszh9A0WhYta fiJYkzcIJiPIKLCngbnwsuVssy2bTyxsHxgDi1bvL/zDHiZ161rQUhgLzp/owPdd1rnD 7xEz4dCTJND5jxcPysUE1e00j1Hqd69xI9cCWTu4lTlu+sBzeEIfUCot4m7uNW6Tj9OW Er1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=p+fm15EhqRyfu1rpg+TS09ifjIYF4eyU99atv4ps14o=; b=fTAMcFDy9tyybrnQdVHFQBa9iSn3WvSwDCXCNsLSL2Qj+AbFtCInTBl2Elsv4LDNBR m8IGo5/Oz4XO/20wCgLhQ2vjT1W5zyCc/zTV9NXf9Te9B0qdO8aSwGnEE7ML/tWpAS3n dCSMza0Wuwfe3jWxkKP6XNAZ1OlgIxIBAo+74TxbHzjUw4L/ICSLNOLotq62JgvhhmY0 UjwysaHb2v5HBCS98G2hXUm88cu2ASmVVJYxpiomJirjD81g3v1JwtdYv6qLOLSQJs2q itA0DBJ5TZ5l0kkCy0jxADEs7PIohwFkHVBpb+aNl7lA0ee9DbiKfmj4MhW7ohM0LG1A UMWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DevstUMG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id b201si3619qkg.491.2017.09.06.07.58.18 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 06 Sep 2017 07:58:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DevstUMG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36556 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpbmS-0003ff-3v for patch@linaro.org; Wed, 06 Sep 2017 10:58:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39965) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpbeN-0005SG-CS for qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpbeL-0000I5-PS for qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:55 -0400 Received: from mail-pg0-x233.google.com ([2607:f8b0:400e:c05::233]:38096) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpbeL-0000Hn-Gp for qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:53 -0400 Received: by mail-pg0-x233.google.com with SMTP id v66so15522895pgb.5 for ; Wed, 06 Sep 2017 07:49:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p+fm15EhqRyfu1rpg+TS09ifjIYF4eyU99atv4ps14o=; b=DevstUMGsCHMFRxETi/tZzR99L2aE7B9qGONjGwqjqAueAUO5qZbT4VcLdtHcJieto oSHO+R03fljUtDQsDDR+/nJbfYSf+X5WqxbzDjNlNBdeSIfEfSKYVvc+g6ExubVzQ3oC 9y5PZDqfxIZKejNGFZFk7nbc1djM1Gg1UYs3I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p+fm15EhqRyfu1rpg+TS09ifjIYF4eyU99atv4ps14o=; b=IiZyWCR8F4QfBoRHK6Bjh/mCRMMhBD9BJnlogSkVcmUaznI6px2FRDALLNVa08kSJV nRHGgiIrId91wQCigdYvZHCyJ6FrMbW0Lq/hvkXm5Rkh2IkhS3GeZwkYy/07T68fHIlW CkkISvd5ge397IArY+15qF4avNJBq8Tm2ULhHMqdUYVMmUFb61pCVSwR+V4Y0641gY1x x7RunHNE0xLbr4fxa4/ndJb0idAdzE2EeDR5AEkgyyA2BX5o4vwJuKiPoKVuPFU97hdc s7Inh7eIpTfZA8rmtZVYWMjmXLHjSUKNTT1hbSPhDBTFlUWG7ImsuUJNRYViekyA59Tx 124A== X-Gm-Message-State: AHPjjUjBgz+YqI9ijhfQlnwvv7oUgBp6eACKaPaiqRXMm8FyIkpwulTf mIXFX1beI0epGCs99qoXAA== X-Google-Smtp-Source: ADKCNb5Io6tNAE87qOU4M0cfRGeo6T0Avv/vMdWciUBXWjGgx5lCfQ+wxu2fegnz65r87GFxysjI4g== X-Received: by 10.99.181.23 with SMTP id y23mr7721360pge.177.1504709392100; Wed, 06 Sep 2017 07:49:52 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id h1sm3467646pfg.153.2017.09.06.07.49.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 07:49:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 07:49:33 -0700 Message-Id: <20170906144940.30880-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906144940.30880-1-richard.henderson@linaro.org> References: <20170906144940.30880-1-richard.henderson@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::233 Subject: [Qemu-devel] [PULL 07/14] tcg/s390: Fully convert tcg_target_op_def X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Use a switch instead of searching a table. Acked-by: Cornelia Huck Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/s390/tcg-target.inc.c | 278 +++++++++++++++++++++++++--------------------- 1 file changed, 154 insertions(+), 124 deletions(-) -- 2.13.5 diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index 5d7083e90c..d34649eb13 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -2246,134 +2246,164 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } } -static const TCGTargetOpDef s390_op_defs[] = { - { INDEX_op_exit_tb, { } }, - { INDEX_op_goto_tb, { } }, - { INDEX_op_br, { } }, - { INDEX_op_goto_ptr, { "r" } }, - - { INDEX_op_ld8u_i32, { "r", "r" } }, - { INDEX_op_ld8s_i32, { "r", "r" } }, - { INDEX_op_ld16u_i32, { "r", "r" } }, - { INDEX_op_ld16s_i32, { "r", "r" } }, - { INDEX_op_ld_i32, { "r", "r" } }, - { INDEX_op_st8_i32, { "r", "r" } }, - { INDEX_op_st16_i32, { "r", "r" } }, - { INDEX_op_st_i32, { "r", "r" } }, - - { INDEX_op_add_i32, { "r", "r", "ri" } }, - { INDEX_op_sub_i32, { "r", "0", "ri" } }, - { INDEX_op_mul_i32, { "r", "0", "rK" } }, - - { INDEX_op_div2_i32, { "b", "a", "0", "1", "r" } }, - { INDEX_op_divu2_i32, { "b", "a", "0", "1", "r" } }, - - { INDEX_op_and_i32, { "r", "0", "ri" } }, - { INDEX_op_or_i32, { "r", "0", "rO" } }, - { INDEX_op_xor_i32, { "r", "0", "rX" } }, - - { INDEX_op_neg_i32, { "r", "r" } }, - - { INDEX_op_shl_i32, { "r", "0", "ri" } }, - { INDEX_op_shr_i32, { "r", "0", "ri" } }, - { INDEX_op_sar_i32, { "r", "0", "ri" } }, - - { INDEX_op_rotl_i32, { "r", "r", "ri" } }, - { INDEX_op_rotr_i32, { "r", "r", "ri" } }, - - { INDEX_op_ext8s_i32, { "r", "r" } }, - { INDEX_op_ext8u_i32, { "r", "r" } }, - { INDEX_op_ext16s_i32, { "r", "r" } }, - { INDEX_op_ext16u_i32, { "r", "r" } }, - - { INDEX_op_bswap16_i32, { "r", "r" } }, - { INDEX_op_bswap32_i32, { "r", "r" } }, - - { INDEX_op_add2_i32, { "r", "r", "0", "1", "rA", "r" } }, - { INDEX_op_sub2_i32, { "r", "r", "0", "1", "rA", "r" } }, - - { INDEX_op_brcond_i32, { "r", "rC" } }, - { INDEX_op_setcond_i32, { "r", "r", "rC" } }, - { INDEX_op_movcond_i32, { "r", "r", "rC", "r", "0" } }, - { INDEX_op_deposit_i32, { "r", "rZ", "r" } }, - { INDEX_op_extract_i32, { "r", "r" } }, - - { INDEX_op_qemu_ld_i32, { "r", "L" } }, - { INDEX_op_qemu_ld_i64, { "r", "L" } }, - { INDEX_op_qemu_st_i32, { "L", "L" } }, - { INDEX_op_qemu_st_i64, { "L", "L" } }, - - { INDEX_op_ld8u_i64, { "r", "r" } }, - { INDEX_op_ld8s_i64, { "r", "r" } }, - { INDEX_op_ld16u_i64, { "r", "r" } }, - { INDEX_op_ld16s_i64, { "r", "r" } }, - { INDEX_op_ld32u_i64, { "r", "r" } }, - { INDEX_op_ld32s_i64, { "r", "r" } }, - { INDEX_op_ld_i64, { "r", "r" } }, - - { INDEX_op_st8_i64, { "r", "r" } }, - { INDEX_op_st16_i64, { "r", "r" } }, - { INDEX_op_st32_i64, { "r", "r" } }, - { INDEX_op_st_i64, { "r", "r" } }, - - { INDEX_op_add_i64, { "r", "r", "ri" } }, - { INDEX_op_sub_i64, { "r", "0", "ri" } }, - { INDEX_op_mul_i64, { "r", "0", "rK" } }, - - { INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } }, - { INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } }, - { INDEX_op_mulu2_i64, { "b", "a", "0", "r" } }, - - { INDEX_op_and_i64, { "r", "0", "ri" } }, - { INDEX_op_or_i64, { "r", "0", "rO" } }, - { INDEX_op_xor_i64, { "r", "0", "rX" } }, - - { INDEX_op_neg_i64, { "r", "r" } }, - - { INDEX_op_shl_i64, { "r", "r", "ri" } }, - { INDEX_op_shr_i64, { "r", "r", "ri" } }, - { INDEX_op_sar_i64, { "r", "r", "ri" } }, - - { INDEX_op_rotl_i64, { "r", "r", "ri" } }, - { INDEX_op_rotr_i64, { "r", "r", "ri" } }, - - { INDEX_op_ext8s_i64, { "r", "r" } }, - { INDEX_op_ext8u_i64, { "r", "r" } }, - { INDEX_op_ext16s_i64, { "r", "r" } }, - { INDEX_op_ext16u_i64, { "r", "r" } }, - { INDEX_op_ext32s_i64, { "r", "r" } }, - { INDEX_op_ext32u_i64, { "r", "r" } }, - - { INDEX_op_ext_i32_i64, { "r", "r" } }, - { INDEX_op_extu_i32_i64, { "r", "r" } }, - - { INDEX_op_bswap16_i64, { "r", "r" } }, - { INDEX_op_bswap32_i64, { "r", "r" } }, - { INDEX_op_bswap64_i64, { "r", "r" } }, - - { INDEX_op_clz_i64, { "r", "r", "ri" } }, - - { INDEX_op_add2_i64, { "r", "r", "0", "1", "rA", "r" } }, - { INDEX_op_sub2_i64, { "r", "r", "0", "1", "rA", "r" } }, - - { INDEX_op_brcond_i64, { "r", "rC" } }, - { INDEX_op_setcond_i64, { "r", "r", "rC" } }, - { INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } }, - { INDEX_op_deposit_i64, { "r", "0", "r" } }, - { INDEX_op_extract_i64, { "r", "r" } }, - - { INDEX_op_mb, { } }, - { -1 }, -}; - static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) { - int i, n = ARRAY_SIZE(s390_op_defs); + static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; + static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; + static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; + static const TCGTargetOpDef L_L = { .args_ct_str = { "L", "L" } }; + static const TCGTargetOpDef r_rC = { .args_ct_str = { "r", "rC" } }; + static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_0_ri = { .args_ct_str = { "r", "0", "ri" } }; + static const TCGTargetOpDef r_0_rK = { .args_ct_str = { "r", "0", "rK" } }; + static const TCGTargetOpDef r_0_rO = { .args_ct_str = { "r", "0", "rO" } }; + static const TCGTargetOpDef r_0_rX = { .args_ct_str = { "r", "0", "rX" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + case INDEX_op_ld_i32: + case INDEX_op_ld32u_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld_i64: + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &r_r; + + case INDEX_op_add_i32: + case INDEX_op_add_i64: + return &r_r_ri; + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + return &r_0_ri; + case INDEX_op_mul_i32: + case INDEX_op_mul_i64: + return &r_0_rK; + case INDEX_op_or_i32: + case INDEX_op_or_i64: + return &r_0_rO; + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + return &r_0_rX; + case INDEX_op_and_i32: + case INDEX_op_and_i64: + return &r_0_ri; + + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + return &r_0_ri; + + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + return &r_r_ri; + + case INDEX_op_rotl_i32: + case INDEX_op_rotl_i64: + case INDEX_op_rotr_i32: + case INDEX_op_rotr_i64: + return &r_r_ri; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &r_rC; + + case INDEX_op_bswap16_i32: + case INDEX_op_bswap16_i64: + case INDEX_op_bswap32_i32: + case INDEX_op_bswap32_i64: + case INDEX_op_bswap64_i64: + case INDEX_op_neg_i32: + case INDEX_op_neg_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_ext_i32_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_extract_i32: + case INDEX_op_extract_i64: + return &r_r; + + case INDEX_op_clz_i64: + return &r_r_ri; + + case INDEX_op_qemu_ld_i32: + case INDEX_op_qemu_ld_i64: + return &r_L; + case INDEX_op_qemu_st_i64: + case INDEX_op_qemu_st_i32: + return &L_L; - for (i = 0; i < n; ++i) { - if (s390_op_defs[i].op == op) { - return &s390_op_defs[i]; + case INDEX_op_deposit_i32: + case INDEX_op_deposit_i64: + { + static const TCGTargetOpDef dep + = { .args_ct_str = { "r", "rZ", "r" } }; + return &dep; } + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + { + static const TCGTargetOpDef setc + = { .args_ct_str = { "r", "r", "rC" } }; + return &setc; + } + case INDEX_op_movcond_i32: + case INDEX_op_movcond_i64: + { + static const TCGTargetOpDef movc + = { .args_ct_str = { "r", "r", "rC", "r", "0" } }; + return &movc; + } + case INDEX_op_div2_i32: + case INDEX_op_div2_i64: + case INDEX_op_divu2_i32: + case INDEX_op_divu2_i64: + { + static const TCGTargetOpDef div2 + = { .args_ct_str = { "b", "a", "0", "1", "r" } }; + return &div2; + } + case INDEX_op_mulu2_i64: + { + static const TCGTargetOpDef mul2 + = { .args_ct_str = { "b", "a", "0", "r" } }; + return &mul2; + } + case INDEX_op_add2_i32: + case INDEX_op_add2_i64: + case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: + { + static const TCGTargetOpDef arith2 + = { .args_ct_str = { "r", "r", "0", "1", "rA", "r" } }; + return &arith2; + } + + default: + break; } return NULL; }