From patchwork Wed Sep 6 14:49:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 111782 Delivered-To: patch@linaro.org Received: by 10.140.94.166 with SMTP id g35csp994204qge; Wed, 6 Sep 2017 07:51:52 -0700 (PDT) X-Received: by 10.80.202.202 with SMTP id f10mr30987edi.14.1504709512380; Wed, 06 Sep 2017 07:51:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1504709512; cv=none; d=google.com; s=arc-20160816; b=Kn45NBecbO0fIwC1YBx9zGroehxDxpOFMj0hW1ehGaEpPycNX2+cOK59Uo9t5O7YHJ asqWV4p2qgqQOQ+VS6PeJxFevmTN3eUEChYEClNTQK5VdiRS+U/94Cq1uKmvDAwOIFcz b9jC1Bcz0yySmZXX/PRrjdgv6UOZXu/4JkqYnXoLZlcRN+LdIM4EuRQW3LMneAk2zJE7 nb8g9ZnIfbTxIimYlg2C1dOwuJWscVQEVYbNM5rmu/tEmawXdFJw2Z5otKH3WsK1eovv min1JUOZjVTN/T/Xvw5T46ElcATU3vYH8P5RDQVi584HDBXEMP5Ow4A8BhGMqaNdeHxz C6pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature:arc-authentication-results; bh=4Wad2p8mSmGPQxF76PMuijqRdg/HPBfOql7iEGJmV70=; b=o84nrehgKMs4aQ3si9ML9Y0H1nt1BZtuaWvykTLNoF2kxcuP47m5JKrADjCjHb7qEQ SnNDxLjvZKY5DJ5um1yAmgKxqzd4zBHBh2xmyZDprfuSYXtb6KFgaCgre6is+MjDql0V rW7Q7xc1yJLNtdd55Wb/oPL1h82IKkCeba1iU1b7rk7kcG+ZpxhxTy30kwiNiyLAnAOb o9frSdyGKBPtFGcfnx4KTMUcYOI591rkCqJVKgqHwjMsFCzgCQ3rxOC9y9BXDPzS9jCI cLQwVkp4Nr4oP8j8yred5ui2PFiH2hAU9RkPgeAOcb31qDfKbt/FF6SG4kWIpNGoB2Lb IgXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ba9okZfI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id z20si3615938edz.7.2017.09.06.07.51.52 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 06 Sep 2017 07:51:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Ba9okZfI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:36528 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpbgF-0006YK-3i for patch@linaro.org; Wed, 06 Sep 2017 10:51:51 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39891) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dpbeG-0005Nm-9j for qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dpbeF-00009k-5B for qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:48 -0400 Received: from mail-pg0-x22a.google.com ([2607:f8b0:400e:c05::22a]:34347) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1dpbeE-00009P-Vn for qemu-devel@nongnu.org; Wed, 06 Sep 2017 10:49:47 -0400 Received: by mail-pg0-x22a.google.com with SMTP id 63so6541097pgc.1 for ; Wed, 06 Sep 2017 07:49:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=4Wad2p8mSmGPQxF76PMuijqRdg/HPBfOql7iEGJmV70=; b=Ba9okZfIYLcgDgzeV5WLw294okb+8R2Wx3FqoTwtC0RourewIH91Za9YOxnOAmtfxG +vaKw6/00jmsDnnfyil5END1FGgbF8yq2C70V2ASB6HWRC5evaCGT1yxaYS2FFl9X3a1 +o2Q9iml87Q8OXWz96rZcuhQvtao+iotC+5+w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=4Wad2p8mSmGPQxF76PMuijqRdg/HPBfOql7iEGJmV70=; b=h95StyLNoA8AwtLYCnb5j3Aj9Ow26spTbnVfESxcnJEJHp/xQ7MtJqHIajvJiMbUVF 6p5ePdo2p2v5GO9L7wWABnGh4V3cJp/AD3JqCQjLvKqvQccdQTgf4saZWtrKzvH+2WLL mZsD3hcDJwA++ql7N/pbpVVE2gsyWqF1WBW2vhWOaIbaD6DmtZcy4naG5wowj3dsYtPi olhGqqNUQ7DXwOq5/pQO8nqrtzP0jLWNSpgrmW6cqhvN6FU4bP3Ubx/hqzxaIxAeoimC 6wdy+BwaymnItnRJBsFgrsvVxbwR4uT5KIxoyMjFObjHLPx5bL1CMILDFsOGFmz7SPC0 DiVw== X-Gm-Message-State: AHPjjUgvnKMVsZE1v8hxAsdxySCU6K+EMbFUKHd7W5Dvd7AjXZ4KGjFS vlCzM72O6/yqnavhIn7S5Q== X-Google-Smtp-Source: ADKCNb5RSJda70ZQ0ceRL5XSdnASKaehImTn+Hoo83yPQ3skQWiR1o9zewyQnGoJa8KaAbSs3bLZjg== X-Received: by 10.98.8.92 with SMTP id c89mr7445384pfd.255.1504709385662; Wed, 06 Sep 2017 07:49:45 -0700 (PDT) Received: from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net. [97.126.108.236]) by smtp.gmail.com with ESMTPSA id h1sm3467646pfg.153.2017.09.06.07.49.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 07:49:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 07:49:28 -0700 Message-Id: <20170906144940.30880-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906144940.30880-1-richard.henderson@linaro.org> References: <20170906144940.30880-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22a Subject: [Qemu-devel] [PULL 02/14] tcg: Add tcg target default memory ordering X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Pranith Kumar Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Pranith Kumar Signed-off-by: Pranith Kumar Message-Id: <20170829063313.10237-3-bobby.prani@gmail.com> [rth: Dropped ia64 hunk] Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/ppc/tcg-target.h | 2 ++ tcg/s390/tcg-target.h | 2 ++ tcg/sparc/tcg-target.h | 2 ++ 6 files changed, 12 insertions(+) -- 2.13.5 diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 55a46ac825..b41a248bee 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -117,4 +117,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) __builtin___clear_cache((char *)start, (char *)stop); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif /* AARCH64_TCG_TARGET_H */ diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 5ef1086710..a38be15a39 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -134,4 +134,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) __builtin___clear_cache((char *) start, (char *) stop); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d75cb63ed3..e9558d15bc 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -206,4 +206,6 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) cacheflush ((void *)start, stop-start, ICACHE); } +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 5f4a40a5b4..5a092b038a 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -125,4 +125,6 @@ extern bool have_isa_3_00; void flush_icache_range(uintptr_t start, uintptr_t stop); +#define TCG_TARGET_DEFAULT_MO (0) + #endif diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h index 957f0c0afe..dc0e59193c 100644 --- a/tcg/s390/tcg-target.h +++ b/tcg/s390/tcg-target.h @@ -133,6 +133,8 @@ extern uint64_t s390_facilities; #define TCG_TARGET_EXTEND_ARGS 1 +#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + enum { TCG_AREG0 = TCG_REG_R10, }; diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 854a0afd70..4515c9ab48 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -162,6 +162,8 @@ extern bool use_vis3_instructions; #define TCG_AREG0 TCG_REG_I0 +#define TCG_TARGET_DEFAULT_MO (0) + static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { uintptr_t p;