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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id l198si8504018qke.24.2017.02.09.09.30.22 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 09 Feb 2017 09:30:22 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39289 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbsY0-0000Vo-8o for patch@linaro.org; Thu, 09 Feb 2017 12:30:20 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60093) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cbsKo-00052m-2U for qemu-devel@nongnu.org; Thu, 09 Feb 2017 12:16:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cbsKk-00055n-6Y for qemu-devel@nongnu.org; Thu, 09 Feb 2017 12:16:42 -0500 Received: from mail-wr0-x22a.google.com ([2a00:1450:400c:c0c::22a]:33308) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cbsKk-00054x-1X for qemu-devel@nongnu.org; Thu, 09 Feb 2017 12:16:38 -0500 Received: by mail-wr0-x22a.google.com with SMTP id i10so88415119wrb.0 for ; Thu, 09 Feb 2017 09:16:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9WRopL73dMmFNBJanC2kSWMZPZMW2vsqOyp5l4UA9Fk=; b=d0uxhdLooxM7WPAXVBzexBLJPoJ4n1KHUUnl+1xlPFgKVw7P5xLoiONvtXdca4tJvW pHtzr4jayl52CVOrwmF1srJbfQ4Sv0VMC3JeECjAt6WHRbFneH10eFcA864S1/aPMbMK YDI/YpnLY2oMpzV/vrSylA7BBY1DbLtPDTMLA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9WRopL73dMmFNBJanC2kSWMZPZMW2vsqOyp5l4UA9Fk=; b=OVg9nEV8bnOcmbQtOlCU/zy+lI1EjixDyNEjUtrGsXEfWui2b1McmqEm+77uGg61Mr eHvLOacN4HdgbgTnlXvSqbDf434Piorue8rYQ3+xK8DIJ+x+647wGsmhzaPTk6Ry0BhR U/NveoDZBeq9nAu2wiS04BYoIJj2tBrSUDE4tYPRgGzGVBRJ3ploWqi1pRnC58+CsQhE ySlHIgwAdHcDBRFaadPt3SdU7aSLOwEcH++VjsubCf4HFXvp35v6wb1JFKaqzHT52QIQ +X1RFAAQf8HY6HEBRKNQ1tibExS0JTmApGKPpPb/0s7U1xWcIlKrYxHc5tvbvN8epNJn y1lw== X-Gm-Message-State: AMke39lzdRUWOwOXFJGM/cD00q3gqQ1d362UyhuTrbjeXPEDzpib8TxVieDe+fXiMEJG7aXn X-Received: by 10.223.148.228 with SMTP id 91mr3712827wrr.37.1486660596929; Thu, 09 Feb 2017 09:16:36 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id o2sm19355520wra.42.2017.02.09.09.16.34 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Feb 2017 09:16:35 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id A59AE3E2D94; Thu, 9 Feb 2017 17:09:06 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: peter.maydell@linaro.org, rth@twiddle.net Date: Thu, 9 Feb 2017 17:09:04 +0000 Message-Id: <20170209170904.5713-25-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170209170904.5713-1-alex.bennee@linaro.org> References: <20170209170904.5713-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c0c::22a Subject: [Qemu-devel] [PATCH v11 24/24] tcg: enable MTTCG by default for ARM on x86 hosts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mttcg@listserver.greensocs.com, nikunj@linux.vnet.ibm.com, jan.kiszka@siemens.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, cota@braap.org, "open list:ARM" , serge.fdrv@gmail.com, pbonzini@redhat.com, bobby.prani@gmail.com, =?utf-8?q?Alex_Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This enables the multi-threaded system emulation by default for ARMv7 and ARMv8 guests using the x86_64 TCG backend. This is because on the guest side: - The ARM translate.c/translate-64.c have been converted to - use MTTCG safe atomic primitives - emit the appropriate barrier ops - The ARM machine has been updated to - hold the BQL when modifying shared cross-vCPU state - defer powerctl changes to async safe work All the host backends support the barrier and atomic primitives but need to provide same-or-better support for normal load/store operations. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Acked-by: Peter Maydell Tested-by: Pranith Kumar Reviewed-by: Pranith Kumar --- v7 - drop configure check for backend - declare backend memory order for x86 - declare guest memory order for ARM - add configure snippet to set TARGET_SUPPORTS_MTTCG v8 - TCG_DEFAULT_MO -> TCG_GUEST_DEFAULT_MO - ~TCG_MO_LD_ST -> ~TCG_MO_ST_LD v10 - moved TCG_DEFAULT_MO -> TCG_GUEST_DEFAULT_MO to original commit v11 - add Pranith's tested/review-by tags - s/defer reset/defer powerctl/ in commit message --- configure | 6 ++++++ target/arm/cpu.h | 3 +++ tcg/i386/tcg-target.h | 11 +++++++++++ 3 files changed, 20 insertions(+) -- 2.11.0 diff --git a/configure b/configure index 86fd833feb..9f2a665f5b 100755 --- a/configure +++ b/configure @@ -5879,6 +5879,7 @@ mkdir -p $target_dir echo "# Automatically generated by configure - do not modify" > $config_target_mak bflt="no" +mttcg="no" interp_prefix1=$(echo "$interp_prefix" | sed "s/%M/$target_name/g") gdb_xml_files="" @@ -5897,11 +5898,13 @@ case "$target_name" in arm|armeb) TARGET_ARCH=arm bflt="yes" + mttcg="yes" gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" ;; aarch64) TARGET_BASE_ARCH=arm bflt="yes" + mttcg="yes" gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" ;; cris) @@ -6066,6 +6069,9 @@ if test "$target_bigendian" = "yes" ; then fi if test "$target_softmmu" = "yes" ; then echo "CONFIG_SOFTMMU=y" >> $config_target_mak + if test "$mttcg" = "yes" ; then + echo "TARGET_SUPPORTS_MTTCG=y" >> $config_target_mak + fi fi if test "$target_user_only" = "yes" ; then echo "CONFIG_USER_ONLY=y" >> $config_target_mak diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f881d1101b..b753463471 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -30,6 +30,9 @@ # define TARGET_LONG_BITS 32 #endif +/* ARM processors have a weak memory model */ +#define TCG_GUEST_DEFAULT_MO (0) + #define CPUArchState struct CPUARMState #include "qemu-common.h" diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 21d96ec35c..4275787db9 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -165,4 +165,15 @@ static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { } +/* This defines the natural memory order supported by this + * architecture before guarantees made by various barrier + * instructions. + * + * The x86 has a pretty strong memory ordering which only really + * allows for some stores to be re-ordered after loads. + */ +#include "tcg-mo.h" + +#define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) + #endif