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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id t20si3286610qtc.316.2017.01.27.03.14.02 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 27 Jan 2017 03:14:02 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:44421 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cX4Tg-00030R-0I for patch@linaro.org; Fri, 27 Jan 2017 06:14:00 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49551) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cX40K-0007cI-37 for qemu-devel@nongnu.org; Fri, 27 Jan 2017 05:43:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cX40J-0004eq-3H for qemu-devel@nongnu.org; Fri, 27 Jan 2017 05:43:40 -0500 Received: from mail-wm0-x229.google.com ([2a00:1450:400c:c09::229]:35318) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cX40I-0004eU-SN for qemu-devel@nongnu.org; Fri, 27 Jan 2017 05:43:38 -0500 Received: by mail-wm0-x229.google.com with SMTP id r126so111091921wmr.0 for ; Fri, 27 Jan 2017 02:43:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J1xpBQjVD3DTVxiV/CC9qQCH9HfTxWdvl37XvN6Emzw=; b=bbEmBMWUG0AREtgvHW9+5BRwqB+BNZ7Abu8w0FnnTyrV1F3yRRQDgYO9ItoF8YGnWO I119F2JL0pvca+ZqELwR55q4ALyknCy1xXvPCAnl9DjSH2v+n7qUXmSv2t66p29bA25o PaBinAaXQd6h9MdlcIugNcelcQiAy4jyYbvtQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J1xpBQjVD3DTVxiV/CC9qQCH9HfTxWdvl37XvN6Emzw=; b=bEzRgYqhzf799AXpFujAHOeKI5Lz8W5obbaZkLo4l1aOKKV0MXtsM7Nct+omoe3/g9 FOO7zivC1/rt50zZ9UC2E5FTIWhJUJoJt1OHgaPsWh3r3nKA123+9OqptgUYALDtFR4H h/XKz/8qx9jVGsSK3udBUl7bybZ7XuU4kQBgaNAgxKOkPaZjLY+Eg7i5MkW4OLjDxUkW IhxKPheZKq2LEQXNo8DHo6N60Zn7RWXF7swKrDI9B6f36mCIl1ZUjgYVLJtPPdxyVky7 P3rVi1hvkjcV6bS0essFgii6B6ECuwaLezo3tuk7UHIXTvDwbaKQ3TINA6cn5vV+OCXG 7eCA== X-Gm-Message-State: AIkVDXIHUk3r5+lAOpHPak8gy0RZ34J+66KpwYLmLqR51ZqXfQs6c3SYLv3lxQRGPCu/o0WD X-Received: by 10.223.160.114 with SMTP id l47mr6666186wrl.73.1485513817799; Fri, 27 Jan 2017 02:43:37 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id y97sm3144084wmh.24.2017.01.27.02.43.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Jan 2017 02:43:33 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 88DFF3E3765; Fri, 27 Jan 2017 10:35:06 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: Date: Fri, 27 Jan 2017 10:34:53 +0000 Message-Id: <20170127103505.18606-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170127103505.18606-1-alex.bennee@linaro.org> References: <20170127103505.18606-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::229 Subject: [Qemu-devel] [PATCH v8 13/25] cputlb: add assert_cpu_is_self checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Richard Henderson , =?utf-8?q?Alex_Benn=C3=A9e?= , "open list:Overall" , Peter Crosthwaite Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For SoftMMU the TLB flushes are an example of a task that can be triggered on one vCPU by another. To deal with this properly we need to use safe work to ensure these changes are done safely. The new assert can be enabled while debugging to catch these cases. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- cputlb.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) -- 2.11.0 diff --git a/cputlb.c b/cputlb.c index 1cc9d9da51..af0e65cd2c 100644 --- a/cputlb.c +++ b/cputlb.c @@ -58,6 +58,12 @@ } \ } while (0) +#define assert_cpu_is_self(this_cpu) do { \ + if (DEBUG_TLB_GATE) { \ + g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \ + } \ + } while (0) + /* statistics */ int tlb_flush_count; @@ -70,6 +76,9 @@ void tlb_flush(CPUState *cpu) { CPUArchState *env = cpu->env_ptr; + assert_cpu_is_self(cpu); + tlb_debug("(count: %d)\n", tlb_flush_count++); + memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); @@ -77,13 +86,13 @@ void tlb_flush(CPUState *cpu) env->vtlb_index = 0; env->tlb_flush_addr = -1; env->tlb_flush_mask = 0; - tlb_flush_count++; } static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp) { CPUArchState *env = cpu->env_ptr; + assert_cpu_is_self(cpu); tlb_debug("start\n"); for (;;) { @@ -128,6 +137,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) int i; int mmu_idx; + assert_cpu_is_self(cpu); tlb_debug("page :" TARGET_FMT_lx "\n", addr); /* Check if we need to flush due to large pages. */ @@ -165,6 +175,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...) va_start(argp, addr); + assert_cpu_is_self(cpu); tlb_debug("addr "TARGET_FMT_lx"\n", addr); /* Check if we need to flush due to large pages. */ @@ -253,6 +264,8 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) int mmu_idx; + assert_cpu_is_self(cpu); + env = cpu->env_ptr; for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; @@ -284,6 +297,8 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) int i; int mmu_idx; + assert_cpu_is_self(cpu); + vaddr &= TARGET_PAGE_MASK; i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { @@ -343,6 +358,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE; int asidx = cpu_asidx_from_attrs(cpu, attrs); + assert_cpu_is_self(cpu); assert(size >= TARGET_PAGE_SIZE); if (size != TARGET_PAGE_SIZE) { tlb_add_large_page(env, vaddr, size);