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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id s12si3020623qtb.66.2017.01.19.09.15.32 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 19 Jan 2017 09:15:32 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49847 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cUGJ7-00077b-Tq for patch@linaro.org; Thu, 19 Jan 2017 12:15:29 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38912) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cUG9V-0007hN-7V for qemu-devel@nongnu.org; Thu, 19 Jan 2017 12:05:34 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cUG9U-0007v7-8o for qemu-devel@nongnu.org; Thu, 19 Jan 2017 12:05:33 -0500 Received: from mail-wm0-x22f.google.com ([2a00:1450:400c:c09::22f]:36601) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cUG9U-0007up-36 for qemu-devel@nongnu.org; Thu, 19 Jan 2017 12:05:32 -0500 Received: by mail-wm0-x22f.google.com with SMTP id c85so2327456wmi.1 for ; Thu, 19 Jan 2017 09:05:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=2TWI1rvb0AHGN29Ld5x568H8swodiKmg2CZG9msgiD8=; b=Bgrq8tw+NBu8CLWbw4oTXirsNLFAn+EXe264xU1bpfZu2UTWv6IWHtopHnblpMBXT5 atQ/Qsb4NPoss5fMVqDxDBlJZBg3STz/XhZwJCDgnRdewJtSyzLSD9+DBzLrU2eLkz8U 4vG+5f8omlMOtxbtLVqxWvTfyRqgIJ4GICUbc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2TWI1rvb0AHGN29Ld5x568H8swodiKmg2CZG9msgiD8=; b=hmXnw/BP+cK1sYkTJp0+1d4XtWCjGXDzDXLG/dC6x1xh5qrMgNHa7bfqrw0ZX8jnDH +ZAjzseF7mTFIIBpVvAj/7rdJRWptKcaHq+tgIZ7PxDzYC7w5b39l00+kZ/xH3huWMto 393BO+SOKx/pqKeZmwyR08wlMuzkih6NMx6LkXSwYwLxA78ww6zWB767qYqXHdxS2Hyq wWN4qUwAEPR5+thoMa+hiAGmcElpzxtEh43IJpAgL+/w6dZ30k5YfahnAcRXUvOJfmcx Y3RlTCtRxCoqzF4KOOqANywZXEIeoTmSFxD4h47kEGvgb/mJd4krui9+6LLfWlnCSdid Rd8g== X-Gm-Message-State: AIkVDXJSJKaSA/avZwt3VznEK47ZQG/Yyn9R8yCF457Qs3Op6xaZFHAeRi0kizO+qQgF+mlh X-Received: by 10.223.177.134 with SMTP id q6mr8325958wra.83.1484845530969; Thu, 19 Jan 2017 09:05:30 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id c81sm14021493wmf.22.2017.01.19.09.05.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jan 2017 09:05:24 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 394B83E2A3C; Thu, 19 Jan 2017 17:05:09 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com Date: Thu, 19 Jan 2017 17:05:00 +0000 Message-Id: <20170119170507.16185-21-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170119170507.16185-1-alex.bennee@linaro.org> References: <20170119170507.16185-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::22f Subject: [Qemu-devel] [PATCH v7 20/27] target-arm: ensure BQL taken for ARM_CP_IO register access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, claudio.fontana@huawei.com, jan.kiszka@siemens.com, mark.burton@greensocs.com, "open list:ARM cores" , serge.fdrv@gmail.com, pbonzini@redhat.com, =?utf-8?q?Alex_Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, rth@twiddle.net Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Most ARMCPRegInfo structures just allow updating of the CPU field. However some have more complex operations that *may* be have cross vCPU effects therefor need to be serialised. The most obvious examples at the moment are things that affect the GICv3 IRQ controller. To avoid applying this requirement to all registers with custom access functions we check for if the type is marked ARM_CP_IO. By default all MMIO access to devices already takes the BQL to serialise hardware emulation. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_cpuif.c | 3 +++ target/arm/op_helper.c | 39 +++++++++++++++++++++++++++++++++++---- 2 files changed, 38 insertions(+), 4 deletions(-) -- 2.11.0 diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 35e8eb30fc..897ae31607 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -13,6 +13,7 @@ */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "trace.h" #include "gicv3_internal.h" #include "cpu.h" @@ -128,6 +129,8 @@ void gicv3_cpuif_update(GICv3CPUState *cs) ARMCPU *cpu = ARM_CPU(cs->cpu); CPUARMState *env = &cpu->env; + g_assert(qemu_mutex_iothread_locked()); + trace_gicv3_cpuif_update(gicv3_redist_affid(cs), cs->hppi.irq, cs->hppi.grp, cs->hppi.prio); diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index ba796d898e..1348789760 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "internals.h" @@ -735,28 +736,58 @@ void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value) { const ARMCPRegInfo *ri = rip; - ri->writefn(env, ri, value); + if (ri->type & ARM_CP_IO) { + qemu_mutex_lock_iothread(); + ri->writefn(env, ri, value); + qemu_mutex_unlock_iothread(); + } else { + ri->writefn(env, ri, value); + } } uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip) { const ARMCPRegInfo *ri = rip; + uint32_t res; - return ri->readfn(env, ri); + if (ri->type & ARM_CP_IO) { + qemu_mutex_lock_iothread(); + res = ri->readfn(env, ri); + qemu_mutex_unlock_iothread(); + } else { + res = ri->readfn(env, ri); + } + + return res; } void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value) { const ARMCPRegInfo *ri = rip; - ri->writefn(env, ri, value); + if (ri->type & ARM_CP_IO) { + qemu_mutex_lock_iothread(); + ri->writefn(env, ri, value); + qemu_mutex_unlock_iothread(); + } else { + ri->writefn(env, ri, value); + } } uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) { const ARMCPRegInfo *ri = rip; + uint64_t res; + + if (ri->type & ARM_CP_IO) { + qemu_mutex_lock_iothread(); + res = ri->readfn(env, ri); + qemu_mutex_unlock_iothread(); + } else { + res = ri->readfn(env, ri); + } - return ri->readfn(env, ri); + return res; } void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)