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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id g80si3037379qkh.151.2017.01.19.09.29.50 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 19 Jan 2017 09:29:50 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:49923 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cUGWy-0003fJ-GX for patch@linaro.org; Thu, 19 Jan 2017 12:29:48 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38832) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cUG9P-0007cI-TU for qemu-devel@nongnu.org; Thu, 19 Jan 2017 12:05:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cUG9O-0007sg-T8 for qemu-devel@nongnu.org; Thu, 19 Jan 2017 12:05:27 -0500 Received: from mail-wm0-x22b.google.com ([2a00:1450:400c:c09::22b]:35621) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cUG9O-0007sM-N0 for qemu-devel@nongnu.org; Thu, 19 Jan 2017 12:05:26 -0500 Received: by mail-wm0-x22b.google.com with SMTP id r126so2397169wmr.0 for ; Thu, 19 Jan 2017 09:05:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=J1xpBQjVD3DTVxiV/CC9qQCH9HfTxWdvl37XvN6Emzw=; b=fTyRXdNpSmfmc2tSPqwn0ghCM+BUrZAQm0GZ139m9qvRlCb4AXyulg8px3MyJM+wDh lUlmb43C2H6WWkylgf8+mixbuR3D2ERvj1ZhQo45L59uAptFddZxjK1yjkXl66HmOf01 WgLB7kyS/hhkADNmY3EagbD/QChFA6bMpKbIA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J1xpBQjVD3DTVxiV/CC9qQCH9HfTxWdvl37XvN6Emzw=; b=lgRuRXMzIANVAEHn8HBmGPwTIfCPJydJ2Myt1VVGy86s0jrHeLBhK0U31EEiUjiwta Gryq8gKy5IvlY2ZZVe4cJJK8waefSv75KwFNqoADSI7NL9rl+kbiH/Hqxltu/E8SZNlq yQMgDaACQDEpHV6rr3Iik90hJNlXCzYCdFpqSRk9Cn9TkvJptZzN7w/2PAk1Y8i+Uog8 m9hJ1GWc3pra0F/WHexWOEalbrPQq/soMNwL/znHBAZwHmRF39c31WFJURxhkJlPQNTY xcZkFoFdaCfaPKTHDbHaWhyhcCHcB2w3Rwa0fP+4SK5jFi5Glp+lNNuMQI4b1Ys+dAAh 1jAQ== X-Gm-Message-State: AIkVDXI6Ye513BGLAQb7AVxY0Qc1+NKLcRRVCdf0JNGRKCLcgJ9OdJBpf8Ed4qKy3p2OAwpo X-Received: by 10.223.134.218 with SMTP id 26mr8142411wry.104.1484845525439; Thu, 19 Jan 2017 09:05:25 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id d64sm54513059wmh.3.2017.01.19.09.05.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Jan 2017 09:05:21 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id AC6E43E2A2C; Thu, 19 Jan 2017 17:05:08 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com, cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com Date: Thu, 19 Jan 2017 17:04:53 +0000 Message-Id: <20170119170507.16185-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170119170507.16185-1-alex.bennee@linaro.org> References: <20170119170507.16185-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::22b Subject: [Qemu-devel] [PATCH v7 13/27] cputlb: add assert_cpu_is_self checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, claudio.fontana@huawei.com, Peter Crosthwaite , jan.kiszka@siemens.com, mark.burton@greensocs.com, serge.fdrv@gmail.com, pbonzini@redhat.com, =?utf-8?q?Alex_Benn=C3=A9e?= , bamvor.zhangjian@linaro.org, rth@twiddle.net Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For SoftMMU the TLB flushes are an example of a task that can be triggered on one vCPU by another. To deal with this properly we need to use safe work to ensure these changes are done safely. The new assert can be enabled while debugging to catch these cases. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- cputlb.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) -- 2.11.0 diff --git a/cputlb.c b/cputlb.c index 1cc9d9da51..af0e65cd2c 100644 --- a/cputlb.c +++ b/cputlb.c @@ -58,6 +58,12 @@ } \ } while (0) +#define assert_cpu_is_self(this_cpu) do { \ + if (DEBUG_TLB_GATE) { \ + g_assert(!cpu->created || qemu_cpu_is_self(cpu)); \ + } \ + } while (0) + /* statistics */ int tlb_flush_count; @@ -70,6 +76,9 @@ void tlb_flush(CPUState *cpu) { CPUArchState *env = cpu->env_ptr; + assert_cpu_is_self(cpu); + tlb_debug("(count: %d)\n", tlb_flush_count++); + memset(env->tlb_table, -1, sizeof(env->tlb_table)); memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table)); memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); @@ -77,13 +86,13 @@ void tlb_flush(CPUState *cpu) env->vtlb_index = 0; env->tlb_flush_addr = -1; env->tlb_flush_mask = 0; - tlb_flush_count++; } static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp) { CPUArchState *env = cpu->env_ptr; + assert_cpu_is_self(cpu); tlb_debug("start\n"); for (;;) { @@ -128,6 +137,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr) int i; int mmu_idx; + assert_cpu_is_self(cpu); tlb_debug("page :" TARGET_FMT_lx "\n", addr); /* Check if we need to flush due to large pages. */ @@ -165,6 +175,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...) va_start(argp, addr); + assert_cpu_is_self(cpu); tlb_debug("addr "TARGET_FMT_lx"\n", addr); /* Check if we need to flush due to large pages. */ @@ -253,6 +264,8 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) int mmu_idx; + assert_cpu_is_self(cpu); + env = cpu->env_ptr; for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { unsigned int i; @@ -284,6 +297,8 @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr) int i; int mmu_idx; + assert_cpu_is_self(cpu); + vaddr &= TARGET_PAGE_MASK; i = (vaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { @@ -343,6 +358,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, unsigned vidx = env->vtlb_index++ % CPU_VTLB_SIZE; int asidx = cpu_asidx_from_attrs(cpu, attrs); + assert_cpu_is_self(cpu); assert(size >= TARGET_PAGE_SIZE); if (size != TARGET_PAGE_SIZE) { tlb_add_large_page(env, vaddr, size);