From patchwork Wed Jan 11 17:35:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laszlo Ersek X-Patchwork-Id: 90981 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp1262937qgi; Wed, 11 Jan 2017 10:46:24 -0800 (PST) X-Received: by 10.200.53.50 with SMTP id y47mr8853750qtb.114.1484160384607; Wed, 11 Jan 2017 10:46:24 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m39si4352118qkh.220.2017.01.11.10.46.24 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 11 Jan 2017 10:46:24 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:56181 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cRNui-0000sT-6e for patch@linaro.org; Wed, 11 Jan 2017 13:46:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42645) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cRMoG-0005jt-5t for qemu-devel@nongnu.org; Wed, 11 Jan 2017 12:35:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cRMoF-0007y3-0h for qemu-devel@nongnu.org; Wed, 11 Jan 2017 12:35:40 -0500 Received: from mx1.redhat.com ([209.132.183.28]:42588) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cRMoE-0007xY-P0 for qemu-devel@nongnu.org; Wed, 11 Jan 2017 12:35:38 -0500 Received: from smtp.corp.redhat.com (int-mx16.intmail.prod.int.phx2.redhat.com [10.5.11.28]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EA39C3B71B for ; Wed, 11 Jan 2017 17:35:38 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-80.phx2.redhat.com [10.3.116.80]) by smtp.corp.redhat.com (Postfix) with ESMTP id 774EC2D655; Wed, 11 Jan 2017 17:35:37 +0000 (UTC) From: Laszlo Ersek To: qemu devel list Date: Wed, 11 Jan 2017 18:35:27 +0100 Message-Id: <20170111173528.30510-3-lersek@redhat.com> In-Reply-To: <20170111173528.30510-1-lersek@redhat.com> References: <20170111173528.30510-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.74 on 10.5.11.28 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Wed, 11 Jan 2017 17:35:38 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH v5 wave 2 2/3] hw/isa/lpc_ich9: add broadcast SMI feature X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor Mammedov , Paolo Bonzini , Gerd Hoffmann , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The generic edk2 SMM infrastructure prefers EFI_SMM_CONTROL2_PROTOCOL.Trigger() to inject an SMI on each processor. If Trigger() only brings the current processor into SMM, then edk2 handles it in the following ways: (1) If Trigger() is executed by the BSP (which is guaranteed before ExitBootServices(), but is not necessarily true at runtime), then: (a) If edk2 has been configured for "traditional" SMM synchronization, then the BSP sends directed SMIs to the APs with APIC delivery, bringing them into SMM individually. Then the BSP runs the SMI handler / dispatcher. (b) If edk2 has been configured for "relaxed" SMM synchronization, then the APs that are not already in SMM are not brought in, and the BSP runs the SMI handler / dispatcher. (2) If Trigger() is executed by an AP (which is possible after ExitBootServices(), and can be forced e.g. by "taskset -c 1 efibootmgr"), then the AP in question brings in the BSP with a directed SMI, and the BSP runs the SMI handler / dispatcher. The smaller problem with (1a) and (2) is that the BSP and AP synchronization is slow. For example, the "taskset -c 1 efibootmgr" command from (2) can take more than 3 seconds to complete, because efibootmgr accesses non-volatile UEFI variables intensively. The larger problem is that QEMU's current behavior diverges from the behavior usually seen on physical hardware, and that keeps exposing obscure corner cases, race conditions and other instabilities in edk2, which generally expects / prefers a software SMI to affect all CPUs at once. Therefore introduce the "broadcast SMI" feature that causes QEMU to inject the SMI on all VCPUs. While the original posting of this patch only intended to speed up (2), based on our recent "stress testing" of SMM this patch actually provides functional improvements. Cc: "Michael S. Tsirkin" Cc: Gerd Hoffmann Cc: Igor Mammedov Cc: Paolo Bonzini Signed-off-by: Laszlo Ersek --- Notes: v5: - replace the ICH9_LPC_SMI_F_BROADCAST bit value with the ICH9_LPC_SMI_F_BROADCAST_BIT bit position (necessary for DEFINE_PROP_BIT() in the next patch) include/hw/i386/ich9.h | 3 +++ hw/isa/lpc_ich9.c | 10 +++++++++- 2 files changed, 12 insertions(+), 1 deletion(-) -- 2.9.3 diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index da1118727146..18dcca7ebcbf 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -250,4 +250,7 @@ Object *ich9_lpc_find(void); #define ICH9_SMB_HST_D1 0x06 #define ICH9_SMB_HOST_BLOCK_DB 0x07 +/* bit positions used in fw_cfg SMI feature negotiation */ +#define ICH9_LPC_SMI_F_BROADCAST_BIT 0 + #endif /* HW_ICH9_H */ diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 376b7801a42c..ced6f803a4f2 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -437,7 +437,15 @@ static void ich9_apm_ctrl_changed(uint32_t val, void *arg) /* SMI_EN = PMBASE + 30. SMI control and enable register */ if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { - cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); + if (lpc->smi_negotiated_features & + (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { + CPUState *cs; + CPU_FOREACH(cs) { + cpu_interrupt(cs, CPU_INTERRUPT_SMI); + } + } else { + cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); + } } }