From patchwork Thu Dec 8 17:50:25 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 87326 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp974947qgi; Thu, 8 Dec 2016 10:01:36 -0800 (PST) X-Received: by 10.200.47.19 with SMTP id j19mr64480195qta.214.1481220096849; Thu, 08 Dec 2016 10:01:36 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id i24si17868052qkh.205.2016.12.08.10.01.36 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Dec 2016 10:01:36 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:48064 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cF30i-0001nC-4G for patch@linaro.org; Thu, 08 Dec 2016 13:01:36 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59860) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cF2qQ-0003eA-80 for qemu-devel@nongnu.org; Thu, 08 Dec 2016 12:50:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cF2qN-0004Dv-5V for qemu-devel@nongnu.org; Thu, 08 Dec 2016 12:50:58 -0500 Received: from mx1.redhat.com ([209.132.183.28]:50712) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cF2qG-00049z-VY; Thu, 08 Dec 2016 12:50:49 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E402F4AEAC; Thu, 8 Dec 2016 17:50:47 +0000 (UTC) Received: from kamzik.brq.redhat.com (kamzik.brq.redhat.com [10.34.1.143]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uB8HoWn6022068; Thu, 8 Dec 2016 12:50:45 -0500 From: Andrew Jones To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Thu, 8 Dec 2016 18:50:25 +0100 Message-Id: <20161208175030.12269-6-drjones@redhat.com> In-Reply-To: <20161208175030.12269-1-drjones@redhat.com> References: <20161208175030.12269-1-drjones@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Thu, 08 Dec 2016 17:50:48 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH kvm-unit-tests v8 05/10] arm/arm64: add initial gicv2 support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, marc.zyngier@arm.com, andre.przywara@arm.com, eric.auger@redhat.com, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add some gicv2 support. This just adds init and enable functions, allowing unit tests to start messing with it. Reviewed-by: Andre Przywara Reviewed-by: Eric Auger Signed-off-by: Andrew Jones --- v6: added comments (register offset headers) [Alex] v5: share/use only the modern register names [Andre] v4: - only take defines from kernel we need now [Andre] - moved defines to asm/gic.h so they'll be shared with v3 [drew] - simplify enable by not caring if we reinit the distributor [drew] - init all GICD_INT_DEF_PRI_X4 registers [Eric] --- arm/Makefile.common | 1 + lib/arm/asm/gic-v2.h | 34 ++++++++++++++++++++++ lib/arm/asm/gic.h | 39 ++++++++++++++++++++++++++ lib/arm64/asm/gic-v2.h | 1 + lib/arm64/asm/gic.h | 1 + lib/arm/gic.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 152 insertions(+) create mode 100644 lib/arm/asm/gic-v2.h create mode 100644 lib/arm/asm/gic.h create mode 100644 lib/arm64/asm/gic-v2.h create mode 100644 lib/arm64/asm/gic.h create mode 100644 lib/arm/gic.c -- 2.9.3 diff --git a/arm/Makefile.common b/arm/Makefile.common index 89fe3f69eb44..0ccd6743a8fe 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -49,6 +49,7 @@ cflatobjs += lib/arm/bitops.o cflatobjs += lib/arm/psci.o cflatobjs += lib/arm/smp.o cflatobjs += lib/arm/delay.o +cflatobjs += lib/arm/gic.o libeabi = lib/arm/libeabi.a eabiobjs = lib/arm/eabi_compat.o diff --git a/lib/arm/asm/gic-v2.h b/lib/arm/asm/gic-v2.h new file mode 100644 index 000000000000..c2d5fecd4886 --- /dev/null +++ b/lib/arm/asm/gic-v2.h @@ -0,0 +1,34 @@ +/* + * All GIC* defines are lifted from include/linux/irqchip/arm-gic.h + * + * Copyright (C) 2016, Red Hat Inc, Andrew Jones + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#ifndef _ASMARM_GIC_V2_H_ +#define _ASMARM_GIC_V2_H_ + +#ifndef _ASMARM_GIC_H_ +#error Do not directly include . Include +#endif + +#define GICD_ENABLE 0x1 +#define GICC_ENABLE 0x1 + +#ifndef __ASSEMBLY__ + +struct gicv2_data { + void *dist_base; + void *cpu_base; + unsigned int irq_nr; +}; +extern struct gicv2_data gicv2_data; + +#define gicv2_dist_base() (gicv2_data.dist_base) +#define gicv2_cpu_base() (gicv2_data.cpu_base) + +extern int gicv2_init(void); +extern void gicv2_enable_defaults(void); + +#endif /* !__ASSEMBLY__ */ +#endif /* _ASMARM_GIC_V2_H_ */ diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h new file mode 100644 index 000000000000..e3580bd1d42d --- /dev/null +++ b/lib/arm/asm/gic.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2016, Red Hat Inc, Andrew Jones + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#ifndef _ASMARM_GIC_H_ +#define _ASMARM_GIC_H_ + +#include + +/* Distributor registers */ +#define GICD_CTLR 0x0000 +#define GICD_TYPER 0x0004 +#define GICD_ISENABLER 0x0100 +#define GICD_IPRIORITYR 0x0400 + +#define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32) +#define GICD_INT_EN_SET_SGI 0x0000ffff +#define GICD_INT_DEF_PRI_X4 0xa0a0a0a0 + +/* CPU interface registers */ +#define GICC_CTLR 0x0000 +#define GICC_PMR 0x0004 + +#define GICC_INT_PRI_THRESHOLD 0xf0 + +#ifndef __ASSEMBLY__ + +/* + * gic_init will try to find all known gics, and then + * initialize the gic data for the one found. + * returns + * 0 : no gic was found + * > 0 : the gic version of the gic found + */ +extern int gic_init(void); + +#endif /* !__ASSEMBLY__ */ +#endif /* _ASMARM_GIC_H_ */ diff --git a/lib/arm64/asm/gic-v2.h b/lib/arm64/asm/gic-v2.h new file mode 100644 index 000000000000..52226624a209 --- /dev/null +++ b/lib/arm64/asm/gic-v2.h @@ -0,0 +1 @@ +#include "../../arm/asm/gic-v2.h" diff --git a/lib/arm64/asm/gic.h b/lib/arm64/asm/gic.h new file mode 100644 index 000000000000..e5eb302a31b4 --- /dev/null +++ b/lib/arm64/asm/gic.h @@ -0,0 +1 @@ +#include "../../arm/asm/gic.h" diff --git a/lib/arm/gic.c b/lib/arm/gic.c new file mode 100644 index 000000000000..d655105e058b --- /dev/null +++ b/lib/arm/gic.c @@ -0,0 +1,76 @@ +/* + * Copyright (C) 2016, Red Hat Inc, Andrew Jones + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#include +#include +#include + +struct gicv2_data gicv2_data; + +/* + * Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt + */ +static bool +gic_get_dt_bases(const char *compatible, void **base1, void **base2) +{ + struct dt_pbus_reg reg; + struct dt_device gic; + struct dt_bus bus; + int node, ret; + + dt_bus_init_defaults(&bus); + dt_device_init(&gic, &bus, NULL); + + node = dt_device_find_compatible(&gic, compatible); + assert(node >= 0 || node == -FDT_ERR_NOTFOUND); + + if (node == -FDT_ERR_NOTFOUND) + return false; + + dt_device_bind_node(&gic, node); + + ret = dt_pbus_translate(&gic, 0, ®); + assert(ret == 0); + *base1 = ioremap(reg.addr, reg.size); + + ret = dt_pbus_translate(&gic, 1, ®); + assert(ret == 0); + *base2 = ioremap(reg.addr, reg.size); + + return true; +} + +int gicv2_init(void) +{ + return gic_get_dt_bases("arm,cortex-a15-gic", + &gicv2_data.dist_base, &gicv2_data.cpu_base); +} + +int gic_init(void) +{ + if (gicv2_init()) + return 2; + return 0; +} + +void gicv2_enable_defaults(void) +{ + void *dist = gicv2_dist_base(); + void *cpu_base = gicv2_cpu_base(); + unsigned int i; + + gicv2_data.irq_nr = GICD_TYPER_IRQS(readl(dist + GICD_TYPER)); + if (gicv2_data.irq_nr > 1020) + gicv2_data.irq_nr = 1020; + + for (i = 0; i < gicv2_data.irq_nr; i += 4) + writel(GICD_INT_DEF_PRI_X4, dist + GICD_IPRIORITYR + i); + + writel(GICD_INT_EN_SET_SGI, dist + GICD_ISENABLER + 0); + writel(GICD_ENABLE, dist + GICD_CTLR); + + writel(GICC_INT_PRI_THRESHOLD, cpu_base + GICC_PMR); + writel(GICC_ENABLE, cpu_base + GICC_CTLR); +}