From patchwork Thu Dec 8 17:50:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 87325 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp974828qgi; Thu, 8 Dec 2016 10:01:25 -0800 (PST) X-Received: by 10.233.216.71 with SMTP id u68mr73237513qkf.161.1481220085186; Thu, 08 Dec 2016 10:01:25 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id b9si17893245qkj.81.2016.12.08.10.01.25 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 08 Dec 2016 10:01:25 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:48063 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cF30W-0000tv-Jj for patch@linaro.org; Thu, 08 Dec 2016 13:01:24 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59751) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cF2qH-00033Y-1B for qemu-devel@nongnu.org; Thu, 08 Dec 2016 12:50:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cF2qE-000492-2x for qemu-devel@nongnu.org; Thu, 08 Dec 2016 12:50:49 -0500 Received: from mx1.redhat.com ([209.132.183.28]:47900) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cF2q9-00045k-AY; Thu, 08 Dec 2016 12:50:41 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 58C5D8F286; Thu, 8 Dec 2016 17:50:40 +0000 (UTC) Received: from kamzik.brq.redhat.com (kamzik.brq.redhat.com [10.34.1.143]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uB8HoWn3022068; Thu, 8 Dec 2016 12:50:38 -0500 From: Andrew Jones To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Thu, 8 Dec 2016 18:50:22 +0100 Message-Id: <20161208175030.12269-3-drjones@redhat.com> In-Reply-To: <20161208175030.12269-1-drjones@redhat.com> References: <20161208175030.12269-1-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Thu, 08 Dec 2016 17:50:40 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [PATCH kvm-unit-tests v8 02/10] arm/arm64: smp: support more than 8 cpus X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, marc.zyngier@arm.com, andre.przywara@arm.com, eric.auger@redhat.com, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" By adding support for launching with gicv3 we can break the 8 vcpu limit. This patch adds support to smp code and also selects the vgic model corresponding to the host. The vgic model may also be manually selected by adding e.g. -machine gic-version=3 to extra_params. Reviewed-by: Alex Bennée Reviewed-by: Andre Przywara Reviewed-by: Eric Auger Signed-off-by: Andrew Jones --- v8: in anticipation of get_mpidr() returning a u64 (patches will be in a future series), make sure we use that type everywhere get_mpidr is used v5: left cpus a u32 for now. Changing to u64 requires a change to devicetree. Will do it later. [Andre] v4: improved commit message --- arm/run | 19 ++++++++++++------- lib/arm/asm/processor.h | 9 +++++++-- lib/arm/asm/setup.h | 4 ++-- lib/arm64/asm/processor.h | 9 +++++++-- arm/selftest.c | 7 ++++++- lib/arm/setup.c | 10 ++++++++++ 6 files changed, 44 insertions(+), 14 deletions(-) -- 2.9.3 diff --git a/arm/run b/arm/run index f1b04af614dc..1c40ab02eb57 100755 --- a/arm/run +++ b/arm/run @@ -31,13 +31,6 @@ if [ -z "$ACCEL" ]; then fi fi -if [ "$HOST" = "aarch64" ] && [ "$ACCEL" = "kvm" ]; then - processor="host" - if [ "$ARCH" = "arm" ]; then - processor+=",aarch64=off" - fi -fi - qemu="${QEMU:-qemu-system-$ARCH_NAME}" qpath=$(which $qemu 2>/dev/null) @@ -53,6 +46,18 @@ fi M='-machine virt' +if [ "$ACCEL" = "kvm" ]; then + if $qemu $M,\? 2>&1 | grep gic-version > /dev/null; then + M+=',gic-version=host' + fi + if [ "$HOST" = "aarch64" ]; then + processor="host" + if [ "$ARCH" = "arm" ]; then + processor+=",aarch64=off" + fi + fi +fi + if ! $qemu $M -device '?' 2>&1 | grep virtconsole > /dev/null; then echo "$qpath doesn't support virtio-console for chr-testdev. Exiting." exit 2 diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h index c831749e04de..6b0d36b87817 100644 --- a/lib/arm/asm/processor.h +++ b/lib/arm/asm/processor.h @@ -40,8 +40,13 @@ static inline unsigned int get_mpidr(void) return read_sysreg(MPIDR); } -/* Only support Aff0 for now, up to 4 cpus */ -#define mpidr_to_cpu(mpidr) ((int)((mpidr) & 0xff)) +#define MPIDR_HWID_BITMASK 0xffffff +extern int mpidr_to_cpu(uint64_t mpidr); + +#define MPIDR_LEVEL_SHIFT(level) \ + (((1 << level) >> 1) << 3) +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff) extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr); extern bool is_user(void); diff --git a/lib/arm/asm/setup.h b/lib/arm/asm/setup.h index cb8fdbd38dd5..1de99dd184d1 100644 --- a/lib/arm/asm/setup.h +++ b/lib/arm/asm/setup.h @@ -10,8 +10,8 @@ #include #include -#define NR_CPUS 8 -extern u32 cpus[NR_CPUS]; +#define NR_CPUS 255 +extern u32 cpus[NR_CPUS]; /* per-cpu IDs (MPIDRs) */ extern int nr_cpus; #define NR_MEM_REGIONS 8 diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h index ed59ad25007b..48abf2c9e358 100644 --- a/lib/arm64/asm/processor.h +++ b/lib/arm64/asm/processor.h @@ -72,8 +72,13 @@ static inline unsigned int get_mpidr(void) return read_sysreg(mpidr_el1); } -/* Only support Aff0 for now, gicv2 only */ -#define mpidr_to_cpu(mpidr) ((int)((mpidr) & 0xff)) +#define MPIDR_HWID_BITMASK 0xff00ffffff +extern int mpidr_to_cpu(uint64_t mpidr); + +#define MPIDR_LEVEL_SHIFT(level) \ + (((1 << level) >> 1) << 3) +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \ + ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff) extern void start_usr(void (*func)(void *arg), void *arg, unsigned long sp_usr); extern bool is_user(void); diff --git a/arm/selftest.c b/arm/selftest.c index 196164f5313d..750e90893141 100644 --- a/arm/selftest.c +++ b/arm/selftest.c @@ -312,9 +312,11 @@ static bool psci_check(void) static cpumask_t smp_reported; static void cpu_report(void) { + uint64_t mpidr = get_mpidr(); int cpu = smp_processor_id(); - report("CPU%d online", true, cpu); + report("CPU(%3d) mpidr=%010" PRIx64, + mpidr_to_cpu(mpidr) == cpu, cpu, mpidr); cpumask_set_cpu(cpu, &smp_reported); halt(); } @@ -343,6 +345,7 @@ int main(int argc, char **argv) } else if (strcmp(argv[1], "smp") == 0) { + uint64_t mpidr = get_mpidr(); int cpu; report("PSCI version", psci_check()); @@ -353,6 +356,8 @@ int main(int argc, char **argv) smp_boot_secondary(cpu, cpu_report); } + report("CPU(%3d) mpidr=%010" PRIx64, + mpidr_to_cpu(mpidr) == 0, 0, mpidr); cpumask_set_cpu(0, &smp_reported); while (!cpumask_full(&smp_reported)) cpu_relax(); diff --git a/lib/arm/setup.c b/lib/arm/setup.c index 7e7b39f11dde..e52a25abd722 100644 --- a/lib/arm/setup.c +++ b/lib/arm/setup.c @@ -30,6 +30,16 @@ int nr_cpus; struct mem_region mem_regions[NR_MEM_REGIONS]; phys_addr_t __phys_offset, __phys_end; +int mpidr_to_cpu(uint64_t mpidr) +{ + int i; + + for (i = 0; i < nr_cpus; ++i) + if (cpus[i] == (mpidr & MPIDR_HWID_BITMASK)) + return i; + return -1; +} + static void cpu_set(int fdtnode __unused, u32 regval, void *info __unused) { int cpu = nr_cpus++;