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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id u123si3461660qkf.273.2016.12.02.09.36.18 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 02 Dec 2016 09:36:18 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35825 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cCrkv-0000BL-Os for patch@linaro.org; Fri, 02 Dec 2016 12:36:17 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60136) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cCrjq-0008IC-By for qemu-devel@nongnu.org; Fri, 02 Dec 2016 12:35:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cCrjn-0001bz-52 for qemu-devel@nongnu.org; Fri, 02 Dec 2016 12:35:10 -0500 Received: from mail-wm0-x235.google.com ([2a00:1450:400c:c09::235]:35642) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cCrjm-0001ao-Ix for qemu-devel@nongnu.org; Fri, 02 Dec 2016 12:35:07 -0500 Received: by mail-wm0-x235.google.com with SMTP id a197so23656093wmd.0 for ; Fri, 02 Dec 2016 09:35:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=e85smq4cZVSxpsoUxY5+e90UTCi0o4jG0+7JjWFi3GI=; b=Rb8XKV1IfcCObvNzkCKHySNtm3ylQ7QvLu9yWJQGyKcGI24E5ie97liTnCwWl58NKV 7+e2QXHWJxs1QJ3eINN2x/bsHfeJaUC94A9zWH+6lp4EOnvm+41ug3TX2541kJpLsLV+ y+jHfzfyp7wbfe9hWXCdmWTE8Il+spPO51M4Y= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=e85smq4cZVSxpsoUxY5+e90UTCi0o4jG0+7JjWFi3GI=; b=UZoACUsZiQtd6Eupzcl/nB4FGmRoRZL8n/jPaYGhFWtwIXkijxEJc9BDvIHxVq5ZSr py7mQI2F10FgKougPWEjhMKmHK79qGD9lWEYDInGV3zVt/5XUZoAYizbKbsB0VtA7vsi 5Q8rhNaOTnZJImO+KdUQaD5RHTdnO4JqF3KRH+plQr+aRCSWtolFfKfJTdqrFeM9hn1v 7xcf9MCmevVgVlRhxHeX0NHiE+Kh6hwyp1fUJufzXHo3Vs+sfQhFsqe9wOZeWFnQI7iJ baahv+Ite4AAzq5MPOaV8uVW0oiNTXyfLrt6zNblKojfFv+9/om4iexCrLR+f+Q77BL+ rM1Q== X-Gm-Message-State: AKaTC02yDRPiE4iUjsNhP+vL/UeGOJNGiGHZveA2UpPxXMxrfadVu7m/Gr8T05jhhlR296Be X-Received: by 10.28.94.76 with SMTP id s73mr4233817wmb.107.1480700103675; Fri, 02 Dec 2016 09:35:03 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id y4sm6675556wjp.0.2016.12.02.09.35.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Dec 2016 09:35:01 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 5B2003E018B; Fri, 2 Dec 2016 17:35:01 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: stefanha@redhat.com, peter.maydell@linaro.org Date: Fri, 2 Dec 2016 17:34:54 +0000 Message-Id: <20161202173454.19179-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.10.2 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::235 Subject: [Qemu-devel] [PATCH for-2.8] target-arm/translate-a64: fix gen_load_exclusive X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cota@braap.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-devel@nongnu.org, "open list:ARM" Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While testing rth's latest TCG patches with risu I found ldaxp was broken. Investigating further I found it was broken by 1dd089d0 when the cmpxchg atomic work was merged. As part of that change the code attempted to be clever by doing a single 64 bit load and then shuffle the data around to set the two 32 bit registers. As I couldn't quite follow the endian magic I've simply partially reverted the change to the original code gen_load_exclusive code. This doesn't affect the cmpxchg functionality as that is all done on in gen_store_exclusive part which is untouched. I've also restored the comment that was removed (with a slight tweak to mention cmpxchg). Signed-off-by: Alex Bennée --- target-arm/translate-a64.c | 42 +++++++++++++++++++----------------------- 1 file changed, 19 insertions(+), 23 deletions(-) -- 2.10.2 Acked-by: Richard Henderson diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index de48747..6dc27a6 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1839,41 +1839,37 @@ static void disas_b_exc_sys(DisasContext *s, uint32_t insn) } } +/* + * Load/Store exclusive instructions are implemented by remembering + * the value/address loaded, and seeing if these are the same + * when the store is performed. This is not actually the architecturally + * mandated semantics, but it works for typical guest code sequences + * and avoids having to monitor regular stores. + * + * The store exclusive uses the atomic cmpxchg primitives to avoid + * races in multi-threaded linux-user and when MTTCG softmmu is + * enabled. + */ static void gen_load_exclusive(DisasContext *s, int rt, int rt2, TCGv_i64 addr, int size, bool is_pair) { TCGv_i64 tmp = tcg_temp_new_i64(); - TCGMemOp be = s->be_data; + TCGMemOp memop = s->be_data + size; g_assert(size <= 3); + tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); + if (is_pair) { + TCGv_i64 addr2 = tcg_temp_new_i64(); TCGv_i64 hitmp = tcg_temp_new_i64(); - if (size == 3) { - TCGv_i64 addr2 = tcg_temp_new_i64(); - - tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), - MO_64 | MO_ALIGN_16 | be); - tcg_gen_addi_i64(addr2, addr, 8); - tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), - MO_64 | MO_ALIGN | be); - tcg_temp_free_i64(addr2); - } else { - g_assert(size == 2); - tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), - MO_64 | MO_ALIGN | be); - if (be == MO_LE) { - tcg_gen_extr32_i64(tmp, hitmp, tmp); - } else { - tcg_gen_extr32_i64(hitmp, tmp, tmp); - } - } - + g_assert(size >= 2); + tcg_gen_addi_i64(addr2, addr, 1 << size); + tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop); + tcg_temp_free_i64(addr2); tcg_gen_mov_i64(cpu_exclusive_high, hitmp); tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp); tcg_temp_free_i64(hitmp); - } else { - tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), size | MO_ALIGN | be); } tcg_gen_mov_i64(cpu_exclusive_val, tmp);