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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id h64si3301666qtd.325.2016.12.02.08.15.27 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 02 Dec 2016 08:15:27 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35369 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cCqUg-0006GS-A6 for patch@linaro.org; Fri, 02 Dec 2016 11:15:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60516) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cCqFa-00030E-Fj for qemu-devel@nongnu.org; Fri, 02 Dec 2016 10:59:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cCqFV-0004xC-Pt for qemu-devel@nongnu.org; Fri, 02 Dec 2016 10:59:50 -0500 Received: from mail-wm0-x235.google.com ([2a00:1450:400c:c09::235]:37972) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cCqFV-0004wf-HB for qemu-devel@nongnu.org; Fri, 02 Dec 2016 10:59:45 -0500 Received: by mail-wm0-x235.google.com with SMTP id f82so19692239wmf.1 for ; Fri, 02 Dec 2016 07:59:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=A+PaY2GKltxE8gMapR3HF8hbIXLAwIPzxSTaNgt4KVQ=; b=PmeItXilw0Q02z+iZEk2NSqCY1eYl0K0TrG4T4NQ0b6UUXb+XsRS8Q89vVHQxrXGzB Oo1jdxqzzW9Qprx/VBX5fN9idubfR8TtFKcCwStWGQUMWMU6tUsBwYIinpmLR8MUnfLF Z9/p31KYwgc/UikUyhxB5lMAITNKmfOu26MgI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A+PaY2GKltxE8gMapR3HF8hbIXLAwIPzxSTaNgt4KVQ=; b=KHrHgGg/d4Vk7pcGGqfMA2giNIGjEMlixK8bh+mG1JBoxvzU7TP7uEm59ORSLsbrTk R+vmj/jrRkTXcsBI8OO4FaLcuH9CCjMznjJhLns0TejXvE+sPEXFKiV+LBOf0mEClaWE xen5iOqAmQlQngvXffXfLgp5FUDbTb1umfyGxQ3QB5bIv0RHBiZZuZxLlglVKwmSBTnV DLusq+eC+Fp1zJ1cfRQEcJi2nvpTMO4VN+FyqlJaTSosHI3FToOpG2+blYXje9+2hDcS 7xA0yg3nUKGnr98+us06kgZYqJd9hGPX/E5gxxIQ9nI8w/hBEU8fn98pep1wer85ca8m /GPQ== X-Gm-Message-State: AKaTC02sXhlLtt93VlJhf/3hLpkf7nCxs04mCBCSXuRYjtWP/0MqSa5xpy8SB1e940AcjLt0 X-Received: by 10.28.164.196 with SMTP id n187mr3546892wme.44.1480694384261; Fri, 02 Dec 2016 07:59:44 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 204sm3879885wmj.7.2016.12.02.07.59.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Dec 2016 07:59:43 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 5F0FE3E033F; Fri, 2 Dec 2016 15:59:40 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: peter.maydell@linaro.org Date: Fri, 2 Dec 2016 15:59:28 +0000 Message-Id: <20161202155935.3130-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161202155935.3130-1-alex.bennee@linaro.org> References: <20161202155935.3130-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::235 Subject: [Qemu-devel] [RISU PATCH 2/9] aarch64: add hand-coded risu skeleton for directed testing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , joserz@linux.vnet.ibm.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Sometimes you want absolute control over your test set-up to feed explicit values into the test. This started as an experiment but might be useful for further developing tests. Signed-off-by: Alex Bennée --- Makefile | 7 ++ aarch64_simd_handcoded.risu.S | 208 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 215 insertions(+) create mode 100644 aarch64_simd_handcoded.risu.S -- 2.10.2 diff --git a/Makefile b/Makefile index bfa8cac..4202c35 100644 --- a/Makefile +++ b/Makefile @@ -36,6 +36,13 @@ $(PROG): $(OBJS) %.risu.asm: %.risu.bin ${OBJDUMP} -b binary -m $(ARCH) -D $^ > $@ +# hand-coded tests +%.risu.bin: %.risu.elf + $(OBJCOPY) -O binary $< $@ + +%.risu.elf: %.risu.S + ${AS} -o $@ $^ + %.o: %.c $(HDRS) $(CC) $(CPPFLAGS) $(CFLAGS) -o $@ -c $< diff --git a/aarch64_simd_handcoded.risu.S b/aarch64_simd_handcoded.risu.S new file mode 100644 index 0000000..61bd11a --- /dev/null +++ b/aarch64_simd_handcoded.risu.S @@ -0,0 +1,208 @@ +/* + Hand coded RISU tests for aarch64 + + Sometimes you want slightly more than random instructions and you + want a specifically crafted test but within RISU's framework. + + This file offers such a thing. + # So the last nibble indicates the desired operation: +my $OP_COMPARE = 0; # compare registers +my $OP_TESTEND = 1; # end of test, stop +my $OP_SETMEMBLOCK = 2; # r0 is address of memory block (8192 bytes) +my $OP_GETMEMBLOCK = 3; # add the address of memory block to r0 +my $OP_COMPAREMEM = 4; # compare memory block + + */ + +.macro risuop_comp + .word 0x00005af0 +.endm +.macro risuop_testend + .word 0x00005af1 +.endm + + .org 0x0 + +//.globl .data + mov x0, #0x0 // #0 + msr fpsr, x0 + mov x0, #0x0 // #0 + msr fpcr, x0 + mrs x0, nzcv + eor w0, w0, #0xf0000000 + msr nzcv, x0 + adr x0, _q0 + eor x0, x0, #0xf + b reg_setup + + /* + + This is the of block of data used for ld/st and setting up vector regs + Each .word is 32bits of data + + */ + .align 16 + +_q0: .word 0x70000000, 0xffffffff, 0x80000000, 0xffffffff +_q1: .word 0x90000000, 0x00000000, 0xa0000000, 0x00000000 +_q2: .word 0xffff0000, 0x00000000, 0xeeee0000, 0x00000000 +_q3: .word 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff +_q4: .word 0x80000000, 0x00000000, 0xf0000000, 0x00000000 +_q5: .word 0xffff0000, 0x00000000, 0xeeee0000, 0x00000000 +_q6: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q7: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 + +_q8: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q9: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q10: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q11: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q12: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q13: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q14: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q15: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 + +_q16: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q17: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q18: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q19: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q20: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q21: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q22: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q23: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 + +_q24: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q25: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q26: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q27: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q28: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q29: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q30: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 +_q31: .word 0x00000000, 0x00000000, 0x00000000, 0x00000000 + + .align 16 + + /* Setup the register state */ +reg_setup: + ldp q0, q1, [x0],#32 + ldp q2, q3, [x0],#16 + ldp q4, q5, [x0],#16 + ldp q6, q7, [x0],#16 + ldp q8, q9, [x0],#16 + ldp q10, q11, [x0],#16 + ldp q12, q13, [x0],#16 + ldp q14, q15, [x0],#16 + ldp q16, q17, [x0],#16 + ldp q18, q19, [x0],#16 + ldp q20, q21, [x0],#16 + ldp q22, q23, [x0],#16 + ldp q24, q25, [x0],#16 + ldp q26, q27, [x0],#16 + ldp q28, q29, [x0],#16 + ldp q30, q31, [x0],#16 + + /* Set-up integer registers */ + mov x0, #0 + mov x1, #0 + mov x2, #0 + mov x3, #0 + mov x4, #0 + mov x5, #0 + mov x6, #0 + mov x7, #0 + mov x8, #0 + mov x9, #0 + mov x10, #0 + mov x11, #0 + mov x12, #0 + mov x13, #0 + mov x14, #0 + mov x15, #0 + mov x16, #0 + mov x17, #0 + mov x18, #0 + mov x19, #0 + mov x20, #0 + mov x21, #0 + mov x22, #0 + mov x23, #0 + mov x24, #0 + mov x25, #0 + mov x26, #0 + mov x26, #0 + mov x27, #0 + mov x28, #0 + mov x29, #0 + mov x30, #0 + + risuop_comp + + /* Testing ursra */ + + ursra v16.2d, v0.2d, #64 + risuop_comp + ursra v17.2d, v1.2d, #64 + risuop_comp + ursra v18.2d, v2.2d, #64 + risuop_comp + ursra v19.2d, v3.2d, #64 + risuop_comp + ursra v20.2d, v4.2d, #64 + risuop_comp + ursra v21.2d, v5.2d, #64 + risuop_comp + ursra v22.2d, v6.2d, #64 + risuop_comp + ursra v23.2d, v7.2d, #64 + risuop_comp + ursra v24.2d, v8.2d, #64 + risuop_comp + ursra v25.2d, v9.2d, #64 + risuop_comp + ursra v26.2d, v10.2d, #64 + risuop_comp + ursra v27.2d, v11.2d, #64 + risuop_comp + ursra v28.2d, v12.2d, #64 + risuop_comp + ursra v29.2d, v13.2d, #64 + risuop_comp + ursra v30.2d, v14.2d, #64 + risuop_comp + ursra v31.2d, v15.2d, #64 + risuop_comp + + /* second pass */ + ursra v16.2d, v0.2d, #64 + risuop_comp + ursra v17.2d, v1.2d, #64 + risuop_comp + ursra v18.2d, v2.2d, #64 + risuop_comp + ursra v19.2d, v3.2d, #64 + risuop_comp + ursra v20.2d, v4.2d, #64 + risuop_comp + ursra v21.2d, v5.2d, #64 + risuop_comp + ursra v22.2d, v6.2d, #64 + risuop_comp + ursra v23.2d, v7.2d, #64 + risuop_comp + ursra v24.2d, v8.2d, #64 + risuop_comp + ursra v25.2d, v9.2d, #64 + risuop_comp + ursra v26.2d, v10.2d, #64 + risuop_comp + ursra v27.2d, v11.2d, #64 + risuop_comp + ursra v28.2d, v12.2d, #64 + risuop_comp + ursra v29.2d, v13.2d, #64 + risuop_comp + ursra v30.2d, v14.2d, #64 + risuop_comp + ursra v31.2d, v15.2d, #64 + risuop_comp + + risuop_testend /* test end */