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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id w3si17942ota.265.2016.11.09.07.15.08 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 09 Nov 2016 07:15:08 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40505 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4Uah-0005u0-FO for patch@linaro.org; Wed, 09 Nov 2016 10:15:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41251) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4UKM-0000jh-VY for qemu-devel@nongnu.org; Wed, 09 Nov 2016 09:58:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c4UKL-0002Me-VC for qemu-devel@nongnu.org; Wed, 09 Nov 2016 09:58:15 -0500 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:38442) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c4UKL-0002MB-OZ for qemu-devel@nongnu.org; Wed, 09 Nov 2016 09:58:13 -0500 Received: by mail-wm0-x22d.google.com with SMTP id f82so247393019wmf.1 for ; Wed, 09 Nov 2016 06:58:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=P9CWnlGfiA4lMSOYiPrKXW9oO7KFD9wFmUGR2+u3dTY=; b=T9sdP6r78y8Jf3MnvMXF5kcl6Mn142LjVko3LMp+oYWTF4biaZ760iK9qJQKzUuE0J FLT5GH4Bo1JmEzeNOhUE601AG5pfv6QKFGLU4ViyWQ3F9iUFYXC0SkaRoBXtDe8qSt+D bbBGHhcryVAknSM1rhRech52lNz4ObinGt8hw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=P9CWnlGfiA4lMSOYiPrKXW9oO7KFD9wFmUGR2+u3dTY=; b=EeAjkx1+PN1zLzTWrPKye45qEcAjyJaD2MQS6MP0YRsl3A6cU/f0ji95h4ok+jTQuP mosjMVqELhSnSSOfKm+dVAPlyqN5h3PGqbmdf7omNtur88TH7Bi4pxFxkmev1gHUNtmk cQL/ARCifC0Q9XsDaNHWskHuoug8dS+HnNJfyj++xS1qpotqlRczIL7ooeZhqJBICI6F nTvQhFxXC/YzdffJ8UJ1GSVnOeuFlqXNo/J/N590gtLyNrS4DwRLD+Yv4hMgprCAHWLA p+Jdd2vz04zt5yNmBzKOhNyW+t7DZMQ9vsSzKB5cuOIKJVXdKUf2e98Fvhvqngc19gW8 oUFA== X-Gm-Message-State: ABUngvczfgB7itht2muLtX9q5gy0y7vXiSCDC44d5MY0AzNAGppOo4Leh3WPSHrd2hQRqbOH X-Received: by 10.194.96.110 with SMTP id dr14mr13541455wjb.209.1478703492463; Wed, 09 Nov 2016 06:58:12 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id n3sm43482896wjq.34.2016.11.09.06.58.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 09 Nov 2016 06:58:05 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 079AB3E04A5; Wed, 9 Nov 2016 14:57:58 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: pbonzini@redhat.com Date: Wed, 9 Nov 2016 14:57:45 +0000 Message-Id: <20161109145748.27282-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161109145748.27282-1-alex.bennee@linaro.org> References: <20161109145748.27282-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::22d Subject: [Qemu-devel] [PATCH v6 16/19] target-arm: ensure BQL taken for ARM_CP_IO register access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mttcg@listserver.greensocs.com, peter.maydell@linaro.org, claudio.fontana@huawei.com, nikunj@linux.vnet.ibm.com, jan.kiszka@siemens.com, mark.burton@greensocs.com, a.rigo@virtualopensystems.com, qemu-devel@nongnu.org, cota@braap.org, "open list:ARM cores" , serge.fdrv@gmail.com, bobby.prani@gmail.com, rth@twiddle.net, =?UTF-8?q?Alex=20Benn=C3=A9e?= , fred.konrad@greensocs.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Most ARMCPRegInfo structures just allow updating of the CPU field. However some have more complex operations that *may* be have cross vCPU effects therefor need to be serialised. The most obvious examples at the moment are things that affect the GICv3 IRQ controller. To avoid applying this requirement to all registers with custom access functions we check for if the type is marked ARM_CP_IO. By default all MMIO access to devices already takes the BQL to serialise hardware emulation. Signed-off-by: Alex Bennée --- hw/intc/arm_gicv3_cpuif.c | 3 +++ target-arm/op_helper.c | 39 +++++++++++++++++++++++++++++++++++---- 2 files changed, 38 insertions(+), 4 deletions(-) -- 2.10.1 Reviewed-by: Richard Henderson diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index bca30c4..8ea4b5b 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -13,6 +13,7 @@ */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "trace.h" #include "gicv3_internal.h" #include "cpu.h" @@ -128,6 +129,8 @@ void gicv3_cpuif_update(GICv3CPUState *cs) ARMCPU *cpu = ARM_CPU(cs->cpu); CPUARMState *env = &cpu->env; + g_assert(qemu_mutex_iothread_locked()); + trace_gicv3_cpuif_update(gicv3_redist_affid(cs), cs->hppi.irq, cs->hppi.grp, cs->hppi.prio); diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index cd94216..4f0c754 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -17,6 +17,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "internals.h" @@ -734,28 +735,58 @@ void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value) { const ARMCPRegInfo *ri = rip; - ri->writefn(env, ri, value); + if (ri->type & ARM_CP_IO) { + qemu_mutex_lock_iothread(); + ri->writefn(env, ri, value); + qemu_mutex_unlock_iothread(); + } else { + ri->writefn(env, ri, value); + } } uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip) { const ARMCPRegInfo *ri = rip; + uint32_t res; - return ri->readfn(env, ri); + if (ri->type & ARM_CP_IO) { + qemu_mutex_lock_iothread(); + res = ri->readfn(env, ri); + qemu_mutex_unlock_iothread(); + } else { + res = ri->readfn(env, ri); + } + + return res; } void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value) { const ARMCPRegInfo *ri = rip; - ri->writefn(env, ri, value); + if (ri->type & ARM_CP_IO) { + qemu_mutex_lock_iothread(); + ri->writefn(env, ri, value); + qemu_mutex_unlock_iothread(); + } else { + ri->writefn(env, ri, value); + } } uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) { const ARMCPRegInfo *ri = rip; + uint64_t res; + + if (ri->type & ARM_CP_IO) { + qemu_mutex_lock_iothread(); + res = ri->readfn(env, ri); + qemu_mutex_unlock_iothread(); + } else { + res = ri->readfn(env, ri); + } - return ri->readfn(env, ri); + return res; } void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)