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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id h4si17737426qtc.54.2016.09.05.07.22.59 for (version=TLS1 cipher=AES128-SHA bits=128/128); Mon, 05 Sep 2016 07:22:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:54948 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bguna-0007L7-La for patch@linaro.org; Mon, 05 Sep 2016 10:22:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34829) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bgubB-00060f-0Y for qemu-devel@nongnu.org; Mon, 05 Sep 2016 10:10:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bgub5-0006sN-Q2 for qemu-devel@nongnu.org; Mon, 05 Sep 2016 10:10:07 -0400 Received: from mail-wm0-x22f.google.com ([2a00:1450:400c:c09::22f]:36714) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bgub4-0006s9-Rw for qemu-devel@nongnu.org; Mon, 05 Sep 2016 10:10:03 -0400 Received: by mail-wm0-x22f.google.com with SMTP id b187so21591841wme.1 for ; Mon, 05 Sep 2016 07:10:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=oOHYd7zbxw/8I9Ha2lxc43vdkXBz94mkngej044+mpg=; b=YGx9MVi4biuCrPyQ7Y+3LKazdrYTTRa+WA3tZnt0t1trZpuwYsBMi/CMTuu0joucCJ Ew/L6Z6q0gn4LoF7QceoFH6cCePK539Tiw1XzgcNt/eAPHqUCxClrBE/btkmYg1GAdK9 ZIfpablnCALtKZKDVCqHm+1L0mdzR9Tv/nHP4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=oOHYd7zbxw/8I9Ha2lxc43vdkXBz94mkngej044+mpg=; b=b5M6AW8+BwCEHykD0H6XctEruykm3Eidqp9vchfwPwFjlU6rUgKEgTfYtACtfRTdG0 FShhhJAbX54molQnEsB3ldHTUlPwPyfpo05ysUDxflXbGWWsqD6xnJQ61czmCBdDI+Re XPgKzXRfvrcXPidvI5uULYewgQ0Az3jqvEl/HsrA7aCyyFzvLaFKO9V6P5bHtyXHxgMm 916xTDl/gph1ozRbY1/rzT4d6ipwauRBhi2E+0TpSyxY3rLL6FHQQshqb9mQYEYrhMgt IXrdN4lx9ZI1x9Jt0677CkY+oTtsyXJMKWf+RNEfJSL6uaJZA1E3L1/Fx5oP/ofFHkjV bSsQ== X-Gm-Message-State: AE9vXwNS4ba6sgsduhYiy6eHZLRjD51pavknBX/yKla7JFKUCPxVVS4MyouoesoXSC/jySz3 X-Received: by 10.28.30.86 with SMTP id e83mr16489288wme.93.1473084602196; Mon, 05 Sep 2016 07:10:02 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id ce6sm27962028wjc.27.2016.09.05.07.10.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Sep 2016 07:10:01 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 590983E0648; Mon, 5 Sep 2016 15:09:55 +0100 (BST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Mon, 5 Sep 2016 15:09:44 +0100 Message-Id: <20160905140944.5379-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.9.3 MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::22f Subject: [Qemu-devel] [RFC PATCH] hw/intc/arm_gic: handle Set-Active/Clear-Active registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, "open list:ARM cores" , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" I noticed while testing with modern kernels and -d guest_errors warnings about invalid writes to the GIC. For GICv2 these registers certainly should work so I've implemented both. As the code is common between all the various GICs writes to GICD_ISACTIVERn is checked to ensure it is not a RO register for v1 GICs. Signed-off-by: Alex Bennée --- hw/intc/arm_gic.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-) -- 2.9.3 diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index b30cc91..423a4ae 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -972,9 +972,38 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK); } } + } else if (offset < 0x380) { + /* Interrupt Set-Active */ + irq = (offset - 0x300) * 8 + GIC_BASE_IRQ; + if (irq >= s->num_irq || s->revision < 2) + goto bad_reg; + + for (i = 0; i < 8; i++) { + if (s->security_extn && !attrs.secure && + !GIC_TEST_GROUP(irq + i, 1 << cpu)) { + continue; /* Ignore Non-secure access of Group0 IRQ */ + } + + if (value & (1 << i)) { + GIC_SET_ACTIVE(irq + i, 1 << cpu); + } + } } else if (offset < 0x400) { - /* Interrupt Active. */ - goto bad_reg; + /* Interrupt Clear-Active */ + irq = (offset - 0x380) * 8 + GIC_BASE_IRQ; + if (irq >= s->num_irq) + goto bad_reg; + + for (i = 0; i < 8; i++) { + if (s->security_extn && !attrs.secure && + !GIC_TEST_GROUP(irq + i, 1 << cpu)) { + continue; /* Ignore Non-secure access of Group0 IRQ */ + } + + if (value & (1 << i)) { + GIC_CLEAR_ACTIVE(irq + i, 1 << cpu); + } + } } else if (offset < 0x800) { /* Interrupt Priority. */ irq = (offset - 0x400) + GIC_BASE_IRQ;