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[77.221.165.98]) by mx.google.com with ESMTPSA id w10sm18189308wia.4.2013.10.23.08.50.58 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Wed, 23 Oct 2013 08:50:58 -0700 (PDT) Date: Wed, 23 Oct 2013 16:50:57 +0100 From: Christoffer Dall To: Peter Maydell Cc: QEMU Developers , "kvmarm@lists.cs.columbia.edu" , Patch Tracking Subject: Re: [RFC PATCH v2 3/6] hw: arm_gic: Keep track of SGI sources Message-ID: <20131023155057.GC60827@lvm> References: <1380229386-24166-1-git-send-email-christoffer.dall@linaro.org> <1380229386-24166-4-git-send-email-christoffer.dall@linaro.org> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.5.21 (2010-09-15) X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: christoffer.dall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Content-Disposition: inline On Mon, Oct 14, 2013 at 05:33:38PM +0100, Peter Maydell wrote: > On 14 October 2013 16:36, Peter Maydell wrote: [...] > > Tangentially, I notice that we don't correctly handle > the PENDING bit for level triggered interrupts, since > we do: > > /* Clear pending flags for both level and edge triggered interrupts. > Level triggered IRQs will be reasserted once they become inactive. */ > gic_clear_pending(s, new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm, > GIC_SGI_SRC(new_irq, cpu)); > > in gic_acknowledge_irq(). This is wrong, because section > 3.2.4 is clear for a level triggered interrupt that if the > interrupt signal remains asserted (which it usually will be) > then we go from Pending to Active+Pending (whereas our > current implementation goes from Pending to Active and > then resets Pending later in gic_complete_irq()). > Yes, I will send this patch to address this as part of the revised series: diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index bf1eb02..fce66c6 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -175,10 +180,15 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu) return 1023; } s->last_active[new_irq][cpu] = s->running_irq[cpu]; - /* Clear pending flags for both level and edge triggered interrupts. - Level triggered IRQs will be reasserted once they become inactive. */ - gic_clear_pending(s, new_irq, GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm, - GIC_SGI_SRC(new_irq, cpu)); + /* Clear pending flags for edge-triggered and non-asserted level-triggered + * interrupts. + */ + cm = GIC_TEST_MODEL(new_irq) ? ALL_CPU_MASK : cm; + if (GIC_TEST_TRIGGER(new_irq) || !GIC_TEST_LEVEL(new_irq, cm)) { + gic_clear_pending(s, new_irq, cm, GIC_SGI_SRC(new_irq, cpu)); + } + gic_set_running_irq(s, cpu, new_irq); DPRINTF("ACK %d\n", new_irq); return new_irq;