From patchwork Thu Oct 29 23:58:42 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taylor Simpson X-Patchwork-Id: 316577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BC160C2D0A3 for ; Fri, 30 Oct 2020 00:19:32 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 09FC220756 for ; Fri, 30 Oct 2020 00:19:29 +0000 (UTC) Authentication-Results: mail.kernel.org; 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Thu, 29 Oct 2020 19:59:11 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1604015943; x=1635551943; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=m+lZZo8zrYMfHUbTWbWGbgG+6XXEcffnvelfRtRKKSo=; b=O3a+oRg6Rkrks1Zas3hqXKfe58E3FFyMpBPGmuejeci4sf5BwXQH1x5k /Itk9JqrtK1P6IkUs5uiKNx1TlHvzPTL7ZySNGZjOyCXEffd+oNUsm4GM 1C4E3+FnNkOqN5W0FgHySiQZ/vlFS5VFPTQrlkPDGie5fkG8WA3a0pcjd 8=; Received: from unknown (HELO ironmsg01-sd.qualcomm.com) ([10.53.140.141]) by alexa-out-sd-01.qualcomm.com with ESMTP; 29 Oct 2020 16:58:55 -0700 X-QCInternal: smtphost Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg01-sd.qualcomm.com with ESMTP; 29 Oct 2020 16:58:55 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 723EE411C; Thu, 29 Oct 2020 18:58:55 -0500 (CDT) From: Taylor Simpson To: tsimpson@quicinc.com Subject: [RFC PATCH v5 25/33] Hexagon (target/hexagon) instruction classes Date: Thu, 29 Oct 2020 18:58:42 -0500 Message-Id: <1604015931-23005-26-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1604015931-23005-1-git-send-email-tsimpson@quicinc.com> References: <1604015931-23005-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/29 19:58:53 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "open list:All patches CC here" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Determine legal VLIW slots for each instruction Signed-off-by: Taylor Simpson --- target/hexagon/iclass.h | 50 ++++++++++++++++++++++++++ target/hexagon/iclass.c | 73 ++++++++++++++++++++++++++++++++++++++ target/hexagon/imported/iclass.def | 51 ++++++++++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100644 target/hexagon/iclass.h create mode 100644 target/hexagon/iclass.c create mode 100644 target/hexagon/imported/iclass.def diff --git a/target/hexagon/iclass.h b/target/hexagon/iclass.h new file mode 100644 index 0000000..b57f11d --- /dev/null +++ b/target/hexagon/iclass.h @@ -0,0 +1,50 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_ICLASS_H +#define HEXAGON_ICLASS_H + +#include "opcodes.h" + +#define ICLASS_FROM_TYPE(TYPE) ICLASS_##TYPE + +enum { + +#define DEF_PP_ICLASS32(TYPE, SLOTS, UNITS) ICLASS_FROM_TYPE(TYPE), +#define DEF_EE_ICLASS32(TYPE, SLOTS, UNITS) ICLASS_FROM_TYPE(TYPE), +#include "imported/iclass.def" +#undef DEF_PP_ICLASS32 +#undef DEF_EE_ICLASS32 + + ICLASS_FROM_TYPE(COPROC_VX), + ICLASS_FROM_TYPE(COPROC_VMEM), + NUM_ICLASSES +}; + +typedef enum { + SLOTS_0 = (1 << 0), + SLOTS_1 = (1 << 1), + SLOTS_2 = (1 << 2), + SLOTS_3 = (1 << 3), + SLOTS_01 = SLOTS_0 | SLOTS_1, + SLOTS_23 = SLOTS_2 | SLOTS_3, + SLOTS_0123 = SLOTS_0 | SLOTS_1 | SLOTS_2 | SLOTS_3, +} SlotMask; + +extern SlotMask find_iclass_slots(Opcode opcode, int itype); + +#endif diff --git a/target/hexagon/iclass.c b/target/hexagon/iclass.c new file mode 100644 index 0000000..05117a9 --- /dev/null +++ b/target/hexagon/iclass.c @@ -0,0 +1,73 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "iclass.h" + +static const SlotMask iclass_info[] = { + +#define DEF_PP_ICLASS32(TYPE, SLOTS, UNITS) \ + [ICLASS_FROM_TYPE(TYPE)] = SLOTS_##SLOTS, +#define DEF_EE_ICLASS32(TYPE, SLOTS, UNITS) \ + [ICLASS_FROM_TYPE(TYPE)] = SLOTS_##SLOTS, +#include "imported/iclass.def" +#undef DEF_PP_ICLASS32 +#undef DEF_EE_ICLASS32 +}; + +SlotMask find_iclass_slots(Opcode opcode, int itype) +{ + /* There are some exceptions to what the iclass dictates */ + if (GET_ATTRIB(opcode, A_ICOP)) { + return SLOTS_2; + } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT0ONLY)) { + return SLOTS_0; + } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT1ONLY)) { + return SLOTS_1; + } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT2ONLY)) { + return SLOTS_2; + } else if (GET_ATTRIB(opcode, A_RESTRICT_SLOT3ONLY)) { + return SLOTS_3; + } else if (GET_ATTRIB(opcode, A_COF) && + GET_ATTRIB(opcode, A_INDIRECT) && + !GET_ATTRIB(opcode, A_MEMLIKE) && + !GET_ATTRIB(opcode, A_MEMLIKE_PACKET_RULES)) { + return SLOTS_2; + } else if (GET_ATTRIB(opcode, A_RESTRICT_NOSLOT1)) { + return SLOTS_0; + } else if ((opcode == J2_trap0) || + (opcode == Y2_isync) || + (opcode == J4_hintjumpr)) { + return SLOTS_2; + } else if ((itype == ICLASS_V2LDST) && (GET_ATTRIB(opcode, A_STORE))) { + return SLOTS_01; + } else if ((itype == ICLASS_V2LDST) && (!GET_ATTRIB(opcode, A_STORE))) { + return SLOTS_01; + } else if (GET_ATTRIB(opcode, A_CRSLOT23)) { + return SLOTS_23; + } else if (GET_ATTRIB(opcode, A_RESTRICT_PREFERSLOT0)) { + return SLOTS_0; + } else if (GET_ATTRIB(opcode, A_SUBINSN)) { + return SLOTS_01; + } else if (GET_ATTRIB(opcode, A_CALL)) { + return SLOTS_23; + } else if ((opcode == J4_jumpseti) || (opcode == J4_jumpsetr)) { + return SLOTS_23; + } else { + return iclass_info[itype]; + } +} diff --git a/target/hexagon/imported/iclass.def b/target/hexagon/imported/iclass.def new file mode 100644 index 0000000..92b0406 --- /dev/null +++ b/target/hexagon/imported/iclass.def @@ -0,0 +1,51 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* DEF_*(TYPE,SLOTS,UNITS) */ +DEF_PP_ICLASS32(EXTENDER,0123,LDST|SUNIT|MUNIT) /* 0 */ +DEF_PP_ICLASS32(CJ,0123,CTRLFLOW) /* 1 */ +DEF_PP_ICLASS32(NCJ,01,LDST|CTRLFLOW) /* 2 */ +DEF_PP_ICLASS32(V4LDST,01,LDST) /* 3 */ +DEF_PP_ICLASS32(V2LDST,01,LDST) /* 4 */ +DEF_PP_ICLASS32(J,0123,CTRLFLOW) /* 5 */ +DEF_PP_ICLASS32(CR,3,SUNIT) /* 6 */ +DEF_PP_ICLASS32(ALU32_2op,0123,LDST|SUNIT|MUNIT) /* 7 */ +DEF_PP_ICLASS32(S_2op,23,SUNIT|MUNIT) /* 8 */ +DEF_PP_ICLASS32(LD,01,LDST) /* 9 */ +DEF_PP_ICLASS32(ST,01,LDST) /* 10 */ +DEF_PP_ICLASS32(ALU32_ADDI,0123,LDST|SUNIT|MUNIT) /* 11 */ +DEF_PP_ICLASS32(S_3op,23,SUNIT|MUNIT) /* 12 */ +DEF_PP_ICLASS32(ALU64,23,SUNIT|MUNIT) /* 13 */ +DEF_PP_ICLASS32(M,23,SUNIT|MUNIT) /* 14 */ +DEF_PP_ICLASS32(ALU32_3op,0123,LDST|SUNIT|MUNIT) /* 15 */ + +DEF_EE_ICLASS32(EE0,01,INVALID) /* 0 */ +DEF_EE_ICLASS32(EE1,01,INVALID) /* 1 */ +DEF_EE_ICLASS32(EE2,01,INVALID) /* 2 */ +DEF_EE_ICLASS32(EE3,01,INVALID) /* 3 */ +DEF_EE_ICLASS32(EE4,01,INVALID) /* 4 */ +DEF_EE_ICLASS32(EE5,01,INVALID) /* 5 */ +DEF_EE_ICLASS32(EE6,01,INVALID) /* 6 */ +DEF_EE_ICLASS32(EE7,01,INVALID) /* 7 */ +DEF_EE_ICLASS32(EE8,01,INVALID) /* 8 */ +DEF_EE_ICLASS32(EE9,01,INVALID) /* 9 */ +DEF_EE_ICLASS32(EEA,01,INVALID) /* 10 */ +DEF_EE_ICLASS32(EEB,01,INVALID) /* 11 */ +DEF_EE_ICLASS32(EEC,01,INVALID) /* 12 */ +DEF_EE_ICLASS32(EED,01,INVALID) /* 13 */ +DEF_EE_ICLASS32(EEE,01,INVALID) /* 14 */ +DEF_EE_ICLASS32(EEF,01,INVALID) /* 15 */