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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id 9sm5031887pjs.1.2020.10.27.22.30.34 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Oct 2020 22:30:36 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 05/10] hw/riscv: microchip_pfsoc: Connect the IOSCB module Date: Wed, 28 Oct 2020 13:30:05 +0800 Message-Id: <1603863010-15807-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1603863010-15807-1-git-send-email-bmeng.cn@gmail.com> References: <1603863010-15807-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Atish Patra , Anup Patel , Ivan Griffin Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Previously IOSCB_CFG was created as an unimplemented device. With the new IOSCB model, its memory range is already covered by the IOSCB hence remove the previous unimplemented device creation in the SoC codes. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) hw/riscv/Kconfig | 1 + hw/riscv/microchip_pfsoc.c | 13 ++++++++----- include/hw/riscv/microchip_pfsoc.h | 4 +++- 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index c8e50bd..8f043e3 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -5,6 +5,7 @@ config MICROCHIP_PFSOC bool select CADENCE_SDHCI select MCHP_PFSOC_DMC + select MCHP_PFSOC_IOSCB select MCHP_PFSOC_MMUART select MSI_NONBROKEN select SIFIVE_CLINT diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 3c504f7..438e0c4 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -16,6 +16,7 @@ * 5) SiFive Platform DMA (Direct Memory Access Controller) * 6) GEM (Gigabit Ethernet MAC Controller) * 7) DMC (DDR Memory Controller) + * 8) IOSCB modules * * This board currently generates devicetree dynamically that indicates at least * two harts and up to five harts. @@ -118,7 +119,7 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_GPIO2] = { 0x20122000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_CFG] = { 0x20200000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_DATA] = { 0x20220000, 0x20000 }, - [MICROCHIP_PFSOC_IOSCB_CFG] = { 0x37080000, 0x1000 }, + [MICROCHIP_PFSOC_IOSCB] = { 0x30000000, 0x10000000 }, [MICROCHIP_PFSOC_DRAM] = { 0x80000000, 0x0 }, }; @@ -162,6 +163,8 @@ static void microchip_pfsoc_soc_instance_init(Object *obj) object_initialize_child(obj, "sd-controller", &s->sdhci, TYPE_CADENCE_SDHCI); + + object_initialize_child(obj, "ioscb", &s->ioscb, TYPE_MCHP_PFSOC_IOSCB); } static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) @@ -373,10 +376,10 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) memmap[MICROCHIP_PFSOC_ENVM_DATA].base, envm_data); - /* IOSCBCFG */ - create_unimplemented_device("microchip.pfsoc.ioscb.cfg", - memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, - memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); + /* IOSCB */ + sysbus_realize(SYS_BUS_DEVICE(&s->ioscb), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ioscb), 0, + memmap[MICROCHIP_PFSOC_IOSCB].base); } static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index 5b81e26..a244ae6 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -25,6 +25,7 @@ #include "hw/char/mchp_pfsoc_mmuart.h" #include "hw/dma/sifive_pdma.h" #include "hw/misc/mchp_pfsoc_dmc.h" +#include "hw/misc/mchp_pfsoc_ioscb.h" #include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" @@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState { DeviceState *plic; MchpPfSoCDdrSgmiiPhyState ddr_sgmii_phy; MchpPfSoCDdrCfgState ddr_cfg; + MchpPfSoCIoscbState ioscb; MchpPfSoCMMUartState *serial0; MchpPfSoCMMUartState *serial1; MchpPfSoCMMUartState *serial2; @@ -99,7 +101,7 @@ enum { MICROCHIP_PFSOC_GPIO2, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, - MICROCHIP_PFSOC_IOSCB_CFG, + MICROCHIP_PFSOC_IOSCB, MICROCHIP_PFSOC_DRAM, };