From patchwork Wed Oct 7 08:39:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: chen huacai X-Patchwork-Id: 303544 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.3 required=3.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_INVALID, DKIM_SIGNED, FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B387C4363C for ; Wed, 7 Oct 2020 08:47:50 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A977921D7A for ; Wed, 7 Oct 2020 08:47:49 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="signature verification failed" (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="IujCPyn3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A977921D7A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:46630 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQ56y-0002Zy-Mv for qemu-devel@archiver.kernel.org; Wed, 07 Oct 2020 04:47:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50496) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQ51e-00075H-Rl for qemu-devel@nongnu.org; Wed, 07 Oct 2020 04:42:19 -0400 Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]:46183) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kQ51b-0002YI-Nl for qemu-devel@nongnu.org; Wed, 07 Oct 2020 04:42:18 -0400 Received: by mail-pg1-x541.google.com with SMTP id 34so915546pgo.13 for ; Wed, 07 Oct 2020 01:42:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XI3/oWaJG+zKphVr0DS9JO4bnux88sWNKgA4LOVVoN0=; b=IujCPyn3BXdlRsJfXUfZjFZhrTEoQ1dpjfYmOXWXzax3k2Q9bhmLHsJaNgZyXnyyOT GUzz7nP0AJLNe02etJQspWq8ekn5yMofUK5ZrLEhP2LKsoVFOpXgMVQiOzcZXnoOG6pe JYi78FEDDB6mDKC5qNW0f75nEDpGYNRpumrgrvly1Mf7aeQJpHUKQS/7VH7vvHS0wZA4 TrK9o2uJUqgUz5BeFwgflhQFwsmBJoxTQ7P1zX3LQC5fY0bvp47s/xRr8ynT1vN3xZ99 HAf1/nCoB2BO6oF8LKt8jvO+jgIBcQ05+tlvYJNoz7cPAgX2lgttJbXMROPcfBU+WKuF y0Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XI3/oWaJG+zKphVr0DS9JO4bnux88sWNKgA4LOVVoN0=; b=XkRYkiqEX/FCw6Om/FEppZJ8tDBd1kdm4FZuQKR8nHQ1ouKDazvFiuCm2bmp/cqjxp d6QGjayfMPZl0X85a9H2+lnM9LcYGq5hGmUtyGWVNxuC0yje7CwteRfQla4EgMlo2PiD b6LEe2c+URibpbzZFtDcPBUQosLQ5futx8U24COe0h0G0Hw2b2FpIbdFL+eYn3A1Dyey ufISa1/N9QF5thE/mGPltLPE4Eo3BRmIvIAvorHgQWHiRQyl0tXGcdHNBLFZNhh85xqy xEyFExch0ekEgCvNrndTqjb4A32nIjZ2X0snPmR6JEb7bmr+TbUZgAxOElysLUooYqga iGZw== X-Gm-Message-State: AOAM533WQb6wl+6jKx/d5Rc7P1jzZyX0t+i7u+EUxFaVjP9vsUw+tstS S7BZIYtikJPcJm5GvHkop4Y= X-Google-Smtp-Source: ABdhPJwg5+f5jBwFOLQQ2LmAYLSEfe2fuQuMoQWDRGOoToee/xNLMjE/48SCy95ZdNR1uKUavknaWA== X-Received: by 2002:a65:6883:: with SMTP id e3mr2052742pgt.250.1602060134495; Wed, 07 Oct 2020 01:42:14 -0700 (PDT) Received: from software.domain.org ([45.77.13.216]) by smtp.gmail.com with ESMTPSA id i9sm1999692pfq.53.2020.10.07.01.42.10 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 Oct 2020 01:42:13 -0700 (PDT) From: Huacai Chen X-Google-Original-From: Huacai Chen To: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aleksandar Markovic Subject: [PATCH V13 3/9] target/mips: Fix PageMask with variable page size Date: Wed, 7 Oct 2020 16:39:29 +0800 Message-Id: <1602059975-10115-4-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1602059975-10115-1-git-send-email-chenhc@lemote.com> References: <1602059975-10115-1-git-send-email-chenhc@lemote.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=zltjiangshi@gmail.com; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , Huacai Chen , qemu-devel@nongnu.org, Jiaxun Yang , Huacai Chen , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Jiaxun Yang Our current code assumed the target page size is always 4k when handling PageMask and VPN2, however, variable page size was just added to mips target and that's no longer true. Fixes: ee3863b9d414 ("target/mips: Support variable page size") Signed-off-by: Huacai Chen Signed-off-by: Jiaxun Yang --- target/mips/cp0_helper.c | 36 +++++++++++++++++++++++++++++------- target/mips/cpu.h | 1 + 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index de64add..f3478d8 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -867,13 +867,35 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1) void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask) { - uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1); - if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) || - (mask == 0x0000 || mask == 0x0003 || mask == 0x000F || - mask == 0x003F || mask == 0x00FF || mask == 0x03FF || - mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) { - env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); + unsigned long mask; + int maskbits; + + if (env->insn_flags & ISA_MIPS32R6) { + return; + } + /* Don't care MASKX as we don't support 1KB page */ + mask = extract32((uint32_t)arg1, CP0PM_MASK, 16); + maskbits = find_first_zero_bit(&mask, 32); + + /* Ensure no more set bit after first zero */ + if (mask >> maskbits) { + goto invalid; + } + /* We don't support VTLB entry smaller than target page */ + if ((maskbits + 12) < TARGET_PAGE_BITS) { + goto invalid; } + env->CP0_PageMask = mask << CP0PM_MASK; + + return; + +invalid: + /* + * When invalid, ensure the value is bigger than or equal to + * the minimal but smaller than or equal to the maxium. + */ + maskbits = MIN(16, MAX(maskbits, TARGET_PAGE_BITS - 12)); + env->CP0_PageMask = ((1 << (16 + 1)) - 1) << CP0PM_MASK; } void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) @@ -1104,7 +1126,7 @@ void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1) void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) { target_ulong old, val, mask; - mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask; + mask = ~((1 << 14) - 1) | env->CP0_EntryHi_ASID_mask; if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) { mask |= 1 << CP0EnHi_EHINV; } diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 7cf7f52..9c8bb23 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -618,6 +618,7 @@ struct CPUMIPSState { * CP0 Register 5 */ int32_t CP0_PageMask; +#define CP0PM_MASK 13 int32_t CP0_PageGrain_rw_bitmask; int32_t CP0_PageGrain; #define CP0PG_RIE 31