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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id l13sm8887520pgq.33.2020.08.31.18.40.25 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 31 Aug 2020 18:40:27 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 01/16] target/riscv: cpu: Add a new 'resetvec' property Date: Tue, 1 Sep 2020 09:38:56 +0800 Message-Id: <1598924352-89526-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598924352-89526-1-git-send-email-bmeng.cn@gmail.com> References: <1598924352-89526-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1041; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1041.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng Currently the reset vector address is hard-coded in a RISC-V CPU's instance_init() routine. In a real world we can have 2 exact same CPUs except for the reset vector address, which is pretty common in the RISC-V core IP licensing business. Normally reset vector address is a configurable parameter. Let's create a 64-bit property to store the reset vector address which covers both 32-bit and 64-bit CPUs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) target/riscv/cpu.h | 1 + target/riscv/cpu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 383808b..dc350f0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -291,6 +291,7 @@ typedef struct RISCVCPU { uint16_t elen; bool mmu; bool pmp; + uint64_t resetvec; } cfg; } RISCVCPU; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 228b9bd..8067a26 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -518,6 +518,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), };