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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.47 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:50 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 Date: Sat, 29 Aug 2020 23:17:36 +0800 Message-Id: <1598714261-8320-13-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=bmeng.cn@gmail.com; helo=mail-ot1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , Jason Wang , Bin Meng , qemu-arm@nongnu.org, "Edgar E. Iglesias" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng When cadence_gem model was created for Xilinx boards, the PHY address was hard-coded to 23 in the GEM model. Now that we have introduced a property we can use that to tell GEM model what our PHY address is. Change all boards' GEM 'phy-addr' property value to 23, and set the PHY address default value to 0 in the GEM model. Signed-off-by: Bin Meng --- (no changes since v1) hw/arm/xilinx_zynq.c | 1 + hw/arm/xlnx-versal.c | 1 + hw/arm/xlnx-zynqmp.c | 1 + hw/net/cadence_gem.c | 6 +++--- 4 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 969ef07..9ffcc56 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -119,6 +119,7 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) qemu_check_nic_model(nd, TYPE_CADENCE_GEM); qdev_set_nic_properties(dev, nd); } + object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); sysbus_mmio_map(s, 0, base); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index e3aa4bd..12ba6c4 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -165,6 +165,7 @@ static void versal_create_gems(Versal *s, qemu_irq *pic) qemu_check_nic_model(nd, "cadence_gem"); qdev_set_nic_properties(dev, nd); } + object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); object_property_set_int(OBJECT(dev), "num-priority-queues", 2, &error_abort); object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c435b9d..a85ef4b 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -460,6 +460,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) } object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISION, &error_abort); + object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues", 2, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index d80096b..7a53469 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -250,7 +250,7 @@ #define GEM_PHYMNTNC_REG_SHIFT 18 /* Marvell PHY definitions */ -#define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */ +#define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at */ #define PHY_REG_CONTROL 0 #define PHY_REG_STATUS 1 @@ -1446,7 +1446,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size) uint32_t phy_addr, reg_num; phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; - if (phy_addr == s->phy_addr || phy_addr == 0) { + if (phy_addr == s->phy_addr) { reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; retval &= 0xFFFF0000; retval |= gem_phy_read(s, reg_num); @@ -1569,7 +1569,7 @@ static void gem_write(void *opaque, hwaddr offset, uint64_t val, uint32_t phy_addr, reg_num; phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT; - if (phy_addr == s->phy_addr || phy_addr == 0) { + if (phy_addr == s->phy_addr) { reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT; gem_phy_write(s, reg_num, val); }