From patchwork Thu Sep 12 16:30:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aleksandar Markovic X-Patchwork-Id: 173722 Delivered-To: patch@linaro.org Received: by 2002:a05:6e02:ce:0:0:0:0 with SMTP id r14csp2374412ilq; Thu, 12 Sep 2019 09:33:57 -0700 (PDT) X-Google-Smtp-Source: APXvYqwV6WkN4A5G5nzABUUUFczNZa3uS6yw3MXK/pBKtBSEOgvtXSdm9b07npQfqM9+Jh0LBLbr X-Received: by 2002:ac8:6916:: with SMTP id e22mr15031730qtr.313.1568306036927; Thu, 12 Sep 2019 09:33:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568306036; cv=none; d=google.com; s=arc-20160816; b=ug7XYyNfHFmH2JuBFzJ7FVgL7QKhQOut5rfOt6CaYTduHx9VxuzVzG0vcP7cHoMyho DpKHYDqBxiV/tqhZCZzJxhwuUKgp/JDNNxNzJ6h0ZxwlXMWwqv1BK1udEuBCuSvHc8MF 7XqSXTptyjMnKO16ws0/QF6KCflOueTA8h7VdDqAFKwiiN7pqP+sQRqDt+DZK2JIGLsF qEGJbdmPp24Sw6qXgjycUlNLHs/IIyNPoshqhxeUYM7ljG6nsV7fi4LIIObdXMV8iVfQ LPrbKhr/YO5HVg2oWiLOf13AQw68jCe6IGlA5mRsFfbHv+zm3c67SY/tmzan+AF7rp+5 uVLg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from; bh=i8LRmxtZuFvq+0UcRSB6Xv3LtsNpoqI8EHl05GHRQcM=; b=wCE/BKpPnX8N0FFKxwnDz58MGnw0fXDrwx1syF9n9tr4AI8PxcrwqTJi6tyYQUgDcT 9kWvO7HuoMM6mGhZT192aNJ5b5e4/Yr/u1LSMFrHIHUtVUVGPAI/+mC5Dy6VeCLPZFWY wG5F7QzpPNFl/ySRLa6SEfzWj+rxNbsGYpNQ8imlMVH6sVHIdax3niy2KuHNrfQ6/NB7 PakQw3DtVvW2WRXN8pAEaXbXFtFkseee9VSCntIVHVyKUzB6kVYgL6QlVx5gFHNxJyCm UsAaTxgThKp8lYLo2VVPrpqGn5uWJ/PFfl65v9jyPCYXekATXNLKEUhlXBXY888btghR uyRw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a66si15549107qkd.192.2019.09.12.09.33.56 for (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 12 Sep 2019 09:33:56 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Received: from localhost ([::1]:36948 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i8S2d-0005pi-MT for patch@linaro.org; Thu, 12 Sep 2019 12:33:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57192) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i8S0g-0005p5-BH for qemu-devel@nongnu.org; Thu, 12 Sep 2019 12:31:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i8S0e-0006KA-Tp for qemu-devel@nongnu.org; Thu, 12 Sep 2019 12:31:54 -0400 Received: from mx2.rt-rk.com ([89.216.37.149]:37117 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i8S0e-00061t-GO for qemu-devel@nongnu.org; Thu, 12 Sep 2019 12:31:52 -0400 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id B78F11A1E6B; Thu, 12 Sep 2019 18:30:46 +0200 (CEST) X-Virus-Scanned: amavisd-new at rt-rk.com Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.13.43]) by mail.rt-rk.com (Postfix) with ESMTPSA id 8C6631A1EA3; Thu, 12 Sep 2019 18:30:46 +0200 (CEST) From: Aleksandar Markovic To: qemu-devel@nongnu.org Date: Thu, 12 Sep 2019 18:30:39 +0200 Message-Id: <1568305840-12550-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1568305840-12550-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1568305840-12550-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 89.216.37.149 Subject: [Qemu-devel] [PULL 3/4] hw/mips/mips_jazz: Remove no-longer-necessary override of do_unassigned_access X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Peter Maydell Now that the MIPS CPU implementation uses the new do_transaction_failed hook, we can remove the old code that handled the do_unassigned_access hook. Signed-off-by: Peter Maydell Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daudé Tested-by: Hervé Poussineau Message-Id: <20190802160458.25681-4-peter.maydell@linaro.org> --- hw/mips/mips_jazz.c | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) -- 2.7.4 diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 1a8e847..c967b97 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -111,18 +111,6 @@ static const MemoryRegionOps dma_dummy_ops = { #define MAGNUM_BIOS_SIZE_MAX 0x7e000 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) -static CPUUnassignedAccess real_do_unassigned_access; -static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, - int opaque, unsigned size) -{ - if (!is_exec) { - /* ignore invalid access (ie do not raise exception) */ - return; - } - (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size); -} - static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr, vaddr addr, unsigned size, MMUAccessType access_type, @@ -184,9 +172,8 @@ static void mips_jazz_init(MachineState *machine, * However, we can't simply add a global memory region to catch * everything, as this would make all accesses including instruction * accesses be ignored and not raise exceptions. - * So instead we hijack either the do_unassigned_access method or - * the do_transaction_failed method on the CPU, and do not raise exceptions - * for data access. + * So instead we hijack the do_transaction_failed method on the CPU, and + * do not raise exceptions for data access. * * NOTE: this behaviour of raising exceptions for bad instruction * fetches but not bad data accesses was added in commit 54e755588cf1e9 @@ -197,14 +184,8 @@ static void mips_jazz_init(MachineState *machine, * memory region that catches all memory accesses, as we do on Malta. */ cc = CPU_GET_CLASS(cpu); - if (cc->do_unassigned_access) { - real_do_unassigned_access = cc->do_unassigned_access; - cc->do_unassigned_access = mips_jazz_do_unassigned_access; - } - if (cc->do_transaction_failed) { - real_do_transaction_failed = cc->do_transaction_failed; - cc->do_transaction_failed = mips_jazz_do_transaction_failed; - } + real_do_transaction_failed = cc->do_transaction_failed; + cc->do_transaction_failed = mips_jazz_do_transaction_failed; /* allocate RAM */ memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",