From patchwork Thu Nov 10 17:21:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 81742 Delivered-To: patch@linaro.org Received: by 10.140.97.165 with SMTP id m34csp873395qge; Thu, 10 Nov 2016 10:26:54 -0800 (PST) X-Received: by 10.202.197.193 with SMTP id v184mr3323911oif.42.1478802414443; Thu, 10 Nov 2016 10:26:54 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [208.118.235.17]) by mx.google.com with ESMTPS id x125si3418607oia.175.2016.11.10.10.26.54 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 10 Nov 2016 10:26:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:48431 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4u3p-0005kq-RN for patch@linaro.org; Thu, 10 Nov 2016 13:26:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56412) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c4t2d-0002r9-Vw for qemu-devel@nongnu.org; Thu, 10 Nov 2016 12:21:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c4t2c-0002oJ-Ix for qemu-devel@nongnu.org; Thu, 10 Nov 2016 12:21:35 -0500 Received: from mx1.redhat.com ([209.132.183.28]:38469) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c4t2Z-0002hR-Sb; Thu, 10 Nov 2016 12:21:31 -0500 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2A6868F032; Thu, 10 Nov 2016 17:21:31 +0000 (UTC) Received: from kamzik.brq.redhat.com (kamzik.brq.redhat.com [10.34.1.143]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id uAAHLMjc006894; Thu, 10 Nov 2016 12:21:28 -0500 From: Andrew Jones To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, qemu-devel@nongnu.org, qemu-arm@nongnu.org Date: Thu, 10 Nov 2016 18:21:12 +0100 Message-Id: <1478798481-25030-3-git-send-email-drjones@redhat.com> In-Reply-To: <1478798481-25030-1-git-send-email-drjones@redhat.com> References: <1478798481-25030-1-git-send-email-drjones@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.26]); Thu, 10 Nov 2016 17:21:31 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [kvm-unit-tests PATCH v5 02/11] arm64: fix get_"sysreg32" and make MPIDR 64bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, marc.zyngier@arm.com, andre.przywara@arm.com, eric.auger@redhat.com, pbonzini@redhat.com, alex.bennee@linaro.org, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" mrs is always 64bit, so we should always use a 64bit register. Sometimes we'll only want to return the lower 32, but not for MPIDR, as that does define fields in the upper 32. Reviewed-by: Alex Bennée Reviewed-by: Eric Auger Signed-off-by: Andrew Jones --- v5: switch arm32's get_mpidr to 'unsigned long' too, to be consistent with arm64 [Andre] --- lib/arm/asm/processor.h | 4 ++-- lib/arm64/asm/processor.h | 15 +++++++++------ 2 files changed, 11 insertions(+), 8 deletions(-) -- 2.7.4 diff --git a/lib/arm/asm/processor.h b/lib/arm/asm/processor.h index f25e7eee3666..02f912f99974 100644 --- a/lib/arm/asm/processor.h +++ b/lib/arm/asm/processor.h @@ -33,9 +33,9 @@ static inline unsigned long current_cpsr(void) #define current_mode() (current_cpsr() & MODE_MASK) -static inline unsigned int get_mpidr(void) +static inline unsigned long get_mpidr(void) { - unsigned int mpidr; + unsigned long mpidr; asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r" (mpidr)); return mpidr; } diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h index 84d5c7ce752b..9a208ff729b7 100644 --- a/lib/arm64/asm/processor.h +++ b/lib/arm64/asm/processor.h @@ -66,14 +66,17 @@ static inline unsigned long current_level(void) return el & 0xc; } -#define DEFINE_GET_SYSREG32(reg) \ -static inline unsigned int get_##reg(void) \ +#define DEFINE_GET_SYSREG(reg, type) \ +static inline type get_##reg(void) \ { \ - unsigned int reg; \ - asm volatile("mrs %0, " #reg "_el1" : "=r" (reg)); \ - return reg; \ + unsigned long r; \ + asm volatile("mrs %0, " #reg "_el1" : "=r" (r)); \ + return (type)r; \ } -DEFINE_GET_SYSREG32(mpidr) +#define DEFINE_GET_SYSREG32(reg) DEFINE_GET_SYSREG(reg, unsigned int) +#define DEFINE_GET_SYSREG64(reg) DEFINE_GET_SYSREG(reg, unsigned long) + +DEFINE_GET_SYSREG64(mpidr) /* Only support Aff0 for now, gicv2 only */ #define mpidr_to_cpu(mpidr) ((int)((mpidr) & 0xff))