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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id a13si5219302qkh.193.2016.07.15.06.14.01 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 15 Jul 2016 06:14:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:60678 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bO2wK-0008HN-Ma for patch@linaro.org; Fri, 15 Jul 2016 09:14:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53528) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bO2k7-00009i-0E for qemu-devel@nongnu.org; Fri, 15 Jul 2016 09:01:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bO2k2-0003OM-Mo for qemu-devel@nongnu.org; Fri, 15 Jul 2016 09:01:23 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37291) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bO2jy-0003NT-H3; Fri, 15 Jul 2016 09:01:14 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id EA2D515555; Fri, 15 Jul 2016 13:01:13 +0000 (UTC) Received: from hawk.localdomain.com (ovpn-204-44.brq.redhat.com [10.40.204.44]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u6FD0gcG018213; Fri, 15 Jul 2016 09:01:11 -0400 From: Andrew Jones To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, pbonzini@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, andre.przywara@arm.com, peter.maydell@linaro.org, alex.bennee@linaro.org Date: Fri, 15 Jul 2016 15:00:41 +0200 Message-Id: <1468587641-7300-11-git-send-email-drjones@redhat.com> In-Reply-To: <1468587641-7300-1-git-send-email-drjones@redhat.com> References: <1468587641-7300-1-git-send-email-drjones@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Fri, 15 Jul 2016 13:01:14 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [kvm-unit-tests PATCH v3 10/10] arm/arm64: gic: don't just use zero X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, eric.auger@redhat.com, wei@redhat.com, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Allow user to select who sends ipis and with which irq, rather than just always sending irq=0 from cpu0. Signed-off-by: Andrew Jones --- v2: actually check that the irq received was the irq sent, and (for gicv2) that the sender is the expected one. --- arm/gic.c | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 64 insertions(+), 16 deletions(-) -- 2.7.4 diff --git a/arm/gic.c b/arm/gic.c index fc7ef241de3e2..d3ab97d4ae470 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -11,6 +11,7 @@ * This work is licensed under the terms of the GNU LGPL, version 2. */ #include +#include #include #include #include @@ -33,6 +34,8 @@ static struct gic *gic; static int gic_version; static int acked[NR_CPUS], spurious[NR_CPUS]; static cpumask_t ready; +static int sender; +static u32 irq; static void nr_cpu_check(int nr) { @@ -85,7 +88,16 @@ static void check_acked(cpumask_t *mask) static u32 gicv2_read_iar(void) { - return readl(gicv2_cpu_base() + GIC_CPU_INTACK); + u32 iar = readl(gicv2_cpu_base() + GIC_CPU_INTACK); + int src = (iar >> 10) & 7; + + if (src != sender) { + report("cpu%d received IPI from unexpected source cpu%d " + "(expected cpu%d)", + false, smp_processor_id(), src, sender); + } + + return iar & 0x3ff; } static void gicv2_write_eoi(u32 irq) @@ -99,9 +111,15 @@ static void ipi_handler(struct pt_regs *regs __unused) if (iar != GICC_INT_SPURIOUS) { gic->write_eoi(iar); - smp_rmb(); /* pairs with wmb in ipi_test functions */ - ++acked[smp_processor_id()]; - smp_wmb(); /* pairs with rmb in check_acked */ + if (iar == irq) { + smp_rmb(); /* pairs with wmb in ipi_test functions */ + ++acked[smp_processor_id()]; + smp_wmb(); /* pairs with rmb in check_acked */ + } else { + report("cpu%d received unexpected irq %u " + "(expected %u)", + false, smp_processor_id(), iar, irq); + } } else { ++spurious[smp_processor_id()]; smp_wmb(); @@ -110,19 +128,19 @@ static void ipi_handler(struct pt_regs *regs __unused) static void gicv2_ipi_send_self(void) { - writel(2 << 24, gicv2_dist_base() + GIC_DIST_SOFTINT); + writel(2 << 24 | irq, gicv2_dist_base() + GIC_DIST_SOFTINT); } static void gicv2_ipi_send_tlist(cpumask_t *mask) { u8 tlist = (u8)cpumask_bits(mask)[0]; - writel(tlist << 16, gicv2_dist_base() + GIC_DIST_SOFTINT); + writel(tlist << 16 | irq, gicv2_dist_base() + GIC_DIST_SOFTINT); } static void gicv2_ipi_send_broadcast(void) { - writel(1 << 24, gicv2_dist_base() + GIC_DIST_SOFTINT); + writel(1 << 24 | irq, gicv2_dist_base() + GIC_DIST_SOFTINT); } #define ICC_SGI1R_AFFINITY_1_SHIFT 16 @@ -165,7 +183,7 @@ static void gicv3_ipi_send_tlist(cpumask_t *mask) sgi1r = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | - /* irq << 24 | */ + irq << 24 | MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | tlist); @@ -187,7 +205,7 @@ static void gicv3_ipi_send_self(void) static void gicv3_ipi_send_broadcast(void) { - gicv3_write_sgi1r(1ULL << 40); + gicv3_write_sgi1r(1ULL << 40 | irq << 24); isb(); } @@ -199,7 +217,7 @@ static void ipi_test_self(void) memset(acked, 0, sizeof(acked)); smp_wmb(); cpumask_clear(&mask); - cpumask_set_cpu(0, &mask); + cpumask_set_cpu(smp_processor_id(), &mask); gic->ipi.send_self(); check_acked(&mask); report_prefix_pop(); @@ -214,7 +232,7 @@ static void ipi_test_smp(void) memset(acked, 0, sizeof(acked)); smp_wmb(); cpumask_copy(&mask, &cpu_present_mask); - for (i = 0; i < nr_cpus; i += 2) + for (i = smp_processor_id() & 1; i < nr_cpus; i += 2) cpumask_clear_cpu(i, &mask); gic->ipi.send_tlist(&mask); check_acked(&mask); @@ -224,7 +242,7 @@ static void ipi_test_smp(void) memset(acked, 0, sizeof(acked)); smp_wmb(); cpumask_copy(&mask, &cpu_present_mask); - cpumask_clear_cpu(0, &mask); + cpumask_clear_cpu(smp_processor_id(), &mask); gic->ipi.send_broadcast(); check_acked(&mask); report_prefix_pop(); @@ -241,6 +259,15 @@ static void ipi_enable(void) local_irq_enable(); } +static void ipi_send(void) +{ + ipi_enable(); + wait_on_ready(); + ipi_test_self(); + ipi_test_smp(); + exit(report_summary()); +} + static void ipi_recv(void) { ipi_enable(); @@ -300,19 +327,40 @@ int main(int argc, char **argv) report_prefix_pop(); } else if (!strcmp(argv[1], "ipi")) { + int off, i = 1; + long val; report_prefix_push(argv[1]); + + while (--argc != 1) { + off = parse_keyval(argv[++i], &val); + if (off == -1) + continue; + argv[i][off] = '\0'; + if (strcmp(argv[i], "sender") == 0) + sender = val; + else if (strcmp(argv[i], "irq") == 0) + irq = val; + } + nr_cpu_check(2); ipi_enable(); for_each_present_cpu(cpu) { if (cpu == 0) continue; - smp_boot_secondary(cpu, ipi_recv); + if (cpu == sender) + smp_boot_secondary(cpu, ipi_send); + else + smp_boot_secondary(cpu, ipi_recv); + } + if (sender == 0) { + wait_on_ready(); + ipi_test_self(); + ipi_test_smp(); + } else { + ipi_recv(); } - wait_on_ready(); - ipi_test_self(); - ipi_test_smp(); smp_rmb(); for_each_present_cpu(cpu) {