From patchwork Sat Jun 4 18:16:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 69327 Delivered-To: patch@linaro.org Received: by 10.140.106.246 with SMTP id e109csp800195qgf; Sat, 4 Jun 2016 11:18:59 -0700 (PDT) X-Received: by 10.55.157.196 with SMTP id g187mr9217046qke.68.1465064338813; Sat, 04 Jun 2016 11:18:58 -0700 (PDT) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id n3si7168488qtd.0.2016.06.04.11.18.58 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 04 Jun 2016 11:18:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:33665 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9G9x-0006nZ-Ru for patch@linaro.org; Sat, 04 Jun 2016 14:18:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51165) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9G7h-0005ZR-58 for qemu-devel@nongnu.org; Sat, 04 Jun 2016 14:16:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b9G7f-0003RB-RV for qemu-devel@nongnu.org; Sat, 04 Jun 2016 14:16:37 -0400 Received: from mx1.redhat.com ([209.132.183.28]:33649) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9G7Y-0003Kx-2D; Sat, 04 Jun 2016 14:16:28 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 870D946295; Sat, 4 Jun 2016 18:16:27 +0000 (UTC) Received: from hawk.localdomain.com (dhcp-1-205.brq.redhat.com [10.34.1.205]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u54IG9nw008070; Sat, 4 Jun 2016 14:16:25 -0400 From: Andrew Jones To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, pbonzini@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, andre.przywara@arm.com, peter.maydell@linaro.org, alex.bennee@linaro.org Date: Sat, 4 Jun 2016 20:16:01 +0200 Message-Id: <1465064165-14885-7-git-send-email-drjones@redhat.com> In-Reply-To: <1465064165-14885-1-git-send-email-drjones@redhat.com> References: <1465064165-14885-1-git-send-email-drjones@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Sat, 04 Jun 2016 18:16:27 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [kvm-unit-tests PATCH v2 06/10] arm/arm64: add initial gicv2 support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add some gicv2 support. This just adds init and enable functions, allowing unit tests to start messing with it. Signed-off-by: Andrew Jones --- arm/Makefile.common | 1 + lib/arm/asm/gic-v2.h | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++ lib/arm/asm/gic.h | 20 ++++++++++++++ lib/arm/gic.c | 69 ++++++++++++++++++++++++++++++++++++++++++++++ lib/arm64/asm/gic-v2.h | 1 + lib/arm64/asm/gic.h | 1 + 6 files changed, 166 insertions(+) create mode 100644 lib/arm/asm/gic-v2.h create mode 100644 lib/arm/asm/gic.h create mode 100644 lib/arm/gic.c create mode 100644 lib/arm64/asm/gic-v2.h create mode 100644 lib/arm64/asm/gic.h -- 2.4.11 diff --git a/arm/Makefile.common b/arm/Makefile.common index a2dc82618b885..0dc9cac241007 100644 --- a/arm/Makefile.common +++ b/arm/Makefile.common @@ -43,6 +43,7 @@ cflatobjs += lib/arm/mmu.o cflatobjs += lib/arm/bitops.o cflatobjs += lib/arm/psci.o cflatobjs += lib/arm/smp.o +cflatobjs += lib/arm/gic.o libeabi = lib/arm/libeabi.a eabiobjs = lib/arm/eabi_compat.o diff --git a/lib/arm/asm/gic-v2.h b/lib/arm/asm/gic-v2.h new file mode 100644 index 0000000000000..973c2bf3cc796 --- /dev/null +++ b/lib/arm/asm/gic-v2.h @@ -0,0 +1,74 @@ +/* + * All GIC* defines are lifted from include/linux/irqchip/arm-gic.h + * + * Copyright (C) 2016, Red Hat Inc, Andrew Jones + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#ifndef _ASMARM_GIC_V2_H_ +#define _ASMARM_GIC_V2_H_ + +#define GIC_CPU_CTRL 0x00 +#define GIC_CPU_PRIMASK 0x04 +#define GIC_CPU_BINPOINT 0x08 +#define GIC_CPU_INTACK 0x0c +#define GIC_CPU_EOI 0x10 +#define GIC_CPU_RUNNINGPRI 0x14 +#define GIC_CPU_HIGHPRI 0x18 +#define GIC_CPU_ALIAS_BINPOINT 0x1c +#define GIC_CPU_ACTIVEPRIO 0xd0 +#define GIC_CPU_IDENT 0xfc +#define GIC_CPU_DEACTIVATE 0x1000 + +#define GICC_ENABLE 0x1 +#define GICC_INT_PRI_THRESHOLD 0xf0 + +#define GIC_CPU_CTRL_EOImodeNS (1 << 9) + +#define GICC_IAR_INT_ID_MASK 0x3ff +#define GICC_INT_SPURIOUS 1023 +#define GICC_DIS_BYPASS_MASK 0x1e0 + +#define GIC_DIST_CTRL 0x000 +#define GIC_DIST_CTR 0x004 +#define GIC_DIST_IGROUP 0x080 +#define GIC_DIST_ENABLE_SET 0x100 +#define GIC_DIST_ENABLE_CLEAR 0x180 +#define GIC_DIST_PENDING_SET 0x200 +#define GIC_DIST_PENDING_CLEAR 0x280 +#define GIC_DIST_ACTIVE_SET 0x300 +#define GIC_DIST_ACTIVE_CLEAR 0x380 +#define GIC_DIST_PRI 0x400 +#define GIC_DIST_TARGET 0x800 +#define GIC_DIST_CONFIG 0xc00 +#define GIC_DIST_SOFTINT 0xf00 +#define GIC_DIST_SGI_PENDING_CLEAR 0xf10 +#define GIC_DIST_SGI_PENDING_SET 0xf20 + +#define GICD_ENABLE 0x1 +#define GICD_DISABLE 0x0 +#define GICD_INT_ACTLOW_LVLTRIG 0x0 +#define GICD_INT_EN_CLR_X32 0xffffffff +#define GICD_INT_EN_SET_SGI 0x0000ffff +#define GICD_INT_EN_CLR_PPI 0xffff0000 +#define GICD_INT_DEF_PRI 0xa0 +#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\ + (GICD_INT_DEF_PRI << 16) |\ + (GICD_INT_DEF_PRI << 8) |\ + GICD_INT_DEF_PRI) +#ifndef __ASSEMBLY__ + +struct gicv2_data { + void *dist_base; + void *cpu_base; +}; +extern struct gicv2_data gicv2_data; + +#define gicv2_dist_base() (gicv2_data.dist_base) +#define gicv2_cpu_base() (gicv2_data.cpu_base) + +extern int gicv2_init(void); +extern void gicv2_enable_defaults(void); + +#endif /* !__ASSEMBLY__ */ +#endif /* _ASMARM_GIC_V2_H_ */ diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h new file mode 100644 index 0000000000000..b1237d1c5ef22 --- /dev/null +++ b/lib/arm/asm/gic.h @@ -0,0 +1,20 @@ +/* + * Copyright (C) 2016, Red Hat Inc, Andrew Jones + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#ifndef _ASMARM_GIC_H_ +#define _ASMARM_GIC_H_ + +#include + +/* + * gic_init will try to find all known gics, and then + * initialize the gic data for the one found. + * returns + * 0 : no gic was found + * > 0 : the gic version of the gic found + */ +extern int gic_init(void); + +#endif /* _ASMARM_GIC_H_ */ diff --git a/lib/arm/gic.c b/lib/arm/gic.c new file mode 100644 index 0000000000000..64a3049c9e8ce --- /dev/null +++ b/lib/arm/gic.c @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2016, Red Hat Inc, Andrew Jones + * + * This work is licensed under the terms of the GNU LGPL, version 2. + */ +#include +#include +#include +#include +#include + +struct gicv2_data gicv2_data; + +/* + * Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt + */ +static bool +gic_get_dt_bases(const char *compatible, void **base1, void **base2) +{ + struct dt_pbus_reg reg; + struct dt_device gic; + struct dt_bus bus; + int node, ret; + + dt_bus_init_defaults(&bus); + dt_device_init(&gic, &bus, NULL); + + node = dt_device_find_compatible(&gic, compatible); + assert(node >= 0 || node == -FDT_ERR_NOTFOUND); + + if (node == -FDT_ERR_NOTFOUND) + return false; + + dt_device_bind_node(&gic, node); + + ret = dt_pbus_translate(&gic, 0, ®); + assert(ret == 0); + *base1 = ioremap(reg.addr, reg.size); + + ret = dt_pbus_translate(&gic, 1, ®); + assert(ret == 0); + *base2 = ioremap(reg.addr, reg.size); + + return true; +} + +int gicv2_init(void) +{ + return gic_get_dt_bases("arm,cortex-a15-gic", + &gicv2_data.dist_base, &gicv2_data.cpu_base); +} + +int gic_init(void) +{ + if (gicv2_init()) + return 2; + return 0; +} + +void gicv2_enable_defaults(void) +{ + if (smp_processor_id() == 0) { + writel(GICD_INT_DEF_PRI_X4, gicv2_dist_base() + GIC_DIST_PRI); + writel(GICD_INT_EN_SET_SGI, gicv2_dist_base() + GIC_DIST_ENABLE_SET); + writel(GICD_ENABLE, gicv2_dist_base() + GIC_DIST_CTRL); + } + writel(GICC_INT_PRI_THRESHOLD, gicv2_cpu_base() + GIC_CPU_PRIMASK); + writel(GICC_ENABLE, gicv2_cpu_base() + GIC_CPU_CTRL); +} diff --git a/lib/arm64/asm/gic-v2.h b/lib/arm64/asm/gic-v2.h new file mode 100644 index 0000000000000..52226624a2092 --- /dev/null +++ b/lib/arm64/asm/gic-v2.h @@ -0,0 +1 @@ +#include "../../arm/asm/gic-v2.h" diff --git a/lib/arm64/asm/gic.h b/lib/arm64/asm/gic.h new file mode 100644 index 0000000000000..e5eb302a31b4d --- /dev/null +++ b/lib/arm64/asm/gic.h @@ -0,0 +1 @@ +#include "../../arm/asm/gic.h"