From patchwork Sat Jun 4 18:15:57 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Andrew Jones X-Patchwork-Id: 69328 Delivered-To: patch@linaro.org Received: by 10.140.106.246 with SMTP id e109csp801127qgf; Sat, 4 Jun 2016 11:22:41 -0700 (PDT) X-Received: by 10.55.15.158 with SMTP id 30mr9170816qkp.31.1465064561352; Sat, 04 Jun 2016 11:22:41 -0700 (PDT) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id m128si6018073qkd.253.2016.06.04.11.22.41 for (version=TLS1 cipher=AES128-SHA bits=128/128); Sat, 04 Jun 2016 11:22:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:33692 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9GDY-0001wC-Pf for patch@linaro.org; Sat, 04 Jun 2016 14:22:40 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51036) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9G7T-0005No-3i for qemu-devel@nongnu.org; Sat, 04 Jun 2016 14:16:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b9G7R-0003E0-5M for qemu-devel@nongnu.org; Sat, 04 Jun 2016 14:16:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45771) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9G7N-00037U-Vk; Sat, 04 Jun 2016 14:16:18 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 98C8163E1F; Sat, 4 Jun 2016 18:16:17 +0000 (UTC) Received: from hawk.localdomain.com (dhcp-1-205.brq.redhat.com [10.34.1.205]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u54IG9ns008070; Sat, 4 Jun 2016 14:16:15 -0400 From: Andrew Jones To: kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu, pbonzini@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, andre.przywara@arm.com, peter.maydell@linaro.org, alex.bennee@linaro.org Date: Sat, 4 Jun 2016 20:15:57 +0200 Message-Id: <1465064165-14885-3-git-send-email-drjones@redhat.com> In-Reply-To: <1465064165-14885-1-git-send-email-drjones@redhat.com> References: <1465064165-14885-1-git-send-email-drjones@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Sat, 04 Jun 2016 18:16:17 +0000 (UTC) X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 209.132.183.28 Subject: [Qemu-devel] [kvm-unit-tests PATCH v2 02/10] arm64: fix get_"sysreg32" and make MPIDR 64bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, christoffer.dall@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" mrs is always 64bit, so we should always use a 64bit register. Sometimes we'll only want to return the lower 32, but not for MPIDR, as that does define fields in the upper 32. Signed-off-by: Andrew Jones --- lib/arm64/asm/processor.h | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) -- 2.4.11 Reviewed-by: Alex Bennée diff --git a/lib/arm64/asm/processor.h b/lib/arm64/asm/processor.h index 84d5c7ce752b0..9a208ff729b7e 100644 --- a/lib/arm64/asm/processor.h +++ b/lib/arm64/asm/processor.h @@ -66,14 +66,17 @@ static inline unsigned long current_level(void) return el & 0xc; } -#define DEFINE_GET_SYSREG32(reg) \ -static inline unsigned int get_##reg(void) \ +#define DEFINE_GET_SYSREG(reg, type) \ +static inline type get_##reg(void) \ { \ - unsigned int reg; \ - asm volatile("mrs %0, " #reg "_el1" : "=r" (reg)); \ - return reg; \ + unsigned long r; \ + asm volatile("mrs %0, " #reg "_el1" : "=r" (r)); \ + return (type)r; \ } -DEFINE_GET_SYSREG32(mpidr) +#define DEFINE_GET_SYSREG32(reg) DEFINE_GET_SYSREG(reg, unsigned int) +#define DEFINE_GET_SYSREG64(reg) DEFINE_GET_SYSREG(reg, unsigned long) + +DEFINE_GET_SYSREG64(mpidr) /* Only support Aff0 for now, gicv2 only */ #define mpidr_to_cpu(mpidr) ((int)((mpidr) & 0xff))