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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id w187si13101678qhw.32.2016.02.26.05.19.08 for (version=TLS1 cipher=AES128-SHA bits=128/128); Fri, 26 Feb 2016 05:19:08 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org; dkim=fail header.i=@linaro.org Received: from localhost ([::1]:49710 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZIIV-0004ZI-PE for patch@linaro.org; Fri, 26 Feb 2016 08:19:07 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33358) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZIFK-0008IP-Cf for qemu-devel@nongnu.org; Fri, 26 Feb 2016 08:15:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aZIFG-0004Dy-1h for qemu-devel@nongnu.org; Fri, 26 Feb 2016 08:15:50 -0500 Received: from mail-wm0-x22d.google.com ([2a00:1450:400c:c09::22d]:38475) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aZIFF-0004Dk-Nh for qemu-devel@nongnu.org; Fri, 26 Feb 2016 08:15:45 -0500 Received: by mail-wm0-x22d.google.com with SMTP id a4so69524411wme.1 for ; Fri, 26 Feb 2016 05:15:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=6dsltBgAuFgwpLRuGUlEz6F5reMDHBPfpct0oo9CpYI=; b=VYzPkF9Ql7Yx9kbX91gJWjkv9ocVKjtAHU9Lg3OdoVolnpIyNiXgJwMGIweCFUiN1/ 2iXZPWurp/BM3FOS7I5AVDV8bw+tSw+vMBPyXXHUb2g58lNUYSW/GzLR+9sDdn3ioEwf Q+lcp4eguoN+uIte2GVAwhWv4e2YHnAFBuxuo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6dsltBgAuFgwpLRuGUlEz6F5reMDHBPfpct0oo9CpYI=; b=hq8AiUKrqooQDmage99KBs8WL5mQ8To7LDpvCSXdvjsXcB7PqCnPpKDR6wcQDd4FNN RhG3/PngZFa7RN7uDlL2CqsnVOMp+443o7/GIIf4tM2HcQGtQzJCLShwPkGDxATC2Jpy qa4wmVeL676vOivO4SyeEGjjv68+5nE/ePetRpMvQNLKix56lmNwSmBq1kJ4SB7BryQG 0rBsLffa3D0jlYmekm4zP1mQza9Pu2GHdF07vSS+YeMdTNDxrMsD36LBHo8C7sqrASeG j/IAtjYipk3svIdv66GRlRLgGaSFdXko7WjmDcc7Wyt1yMOWQEFCDn6UADhkEczYTsvL ccXQ== X-Gm-Message-State: AD7BkJJO0SRs2EpFVxxkq6q393dPxU6khTdA+tLA/1Q9zhQkQyko3gsHvhhkf2VUZhS1jfIV X-Received: by 10.194.185.199 with SMTP id fe7mr1708948wjc.50.1456492545211; Fri, 26 Feb 2016 05:15:45 -0800 (PST) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id x65sm2879824wmg.4.2016.02.26.05.15.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 26 Feb 2016 05:15:41 -0800 (PST) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 454173E0218; Fri, 26 Feb 2016 13:15:41 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: mttcg@listserver.greensocs.com, mark.burton@greensocs.com, fred.konrad@greensocs.com, a.rigo@virtualopensystems.com Date: Fri, 26 Feb 2016 13:15:25 +0000 Message-Id: <1456492533-17171-4-git-send-email-alex.bennee@linaro.org> X-Mailer: git-send-email 2.7.1 In-Reply-To: <1456492533-17171-1-git-send-email-alex.bennee@linaro.org> References: <1456492533-17171-1-git-send-email-alex.bennee@linaro.org> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::22d Cc: peter.maydell@linaro.org, drjones@redhat.com, a.spyridakis@virtualopensystems.com, claudio.fontana@huawei.com, qemu-devel@nongnu.org, will.deacon@arm.com, crosthwaitepeter@gmail.com, pbonzini@redhat.com, aurelien@aurel32.net, rth@twiddle.net Subject: [Qemu-devel] [RFC 03/11] arm/arm64: Add initial gic support X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Andrew Jones Add some gic(v2) support. This just adds enough support for an IPI test. It's really just a starting point, and the general functions (inlines in gic.h) may need some changes as more support is added. Signed-off-by: Andrew Jones --- lib/arm/asm/gic.h | 122 ++++++++++++++++++++++++++++++++++++++++++++++++++++ lib/arm/io.c | 31 +++++++++++++ lib/arm64/asm/gic.h | 1 + 3 files changed, 154 insertions(+) create mode 100644 lib/arm/asm/gic.h create mode 100644 lib/arm64/asm/gic.h -- 2.7.1 diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h new file mode 100644 index 0000000..6f27c91 --- /dev/null +++ b/lib/arm/asm/gic.h @@ -0,0 +1,122 @@ +/* + * Copyright (C) 2015, Red Hat Inc, Andrew Jones + * + * This work is licensed under the terms of the GNU LGPL, version 2. + * + * All GIC* defines are lifted from include/linux/irqchip/arm-gic.h + */ +#ifndef _ASMARM_GIC_H_ +#define _ASMARM_GIC_H_ + +#define GIC_CPU_CTRL 0x00 +#define GIC_CPU_PRIMASK 0x04 +#define GIC_CPU_BINPOINT 0x08 +#define GIC_CPU_INTACK 0x0c +#define GIC_CPU_EOI 0x10 +#define GIC_CPU_RUNNINGPRI 0x14 +#define GIC_CPU_HIGHPRI 0x18 +#define GIC_CPU_ALIAS_BINPOINT 0x1c +#define GIC_CPU_ACTIVEPRIO 0xd0 +#define GIC_CPU_IDENT 0xfc + +#define GICC_ENABLE 0x1 +#define GICC_INT_PRI_THRESHOLD 0xf0 +#define GICC_IAR_INT_ID_MASK 0x3ff +#define GICC_INT_SPURIOUS 1023 +#define GICC_DIS_BYPASS_MASK 0x1e0 + +#define GIC_DIST_CTRL 0x000 +#define GIC_DIST_CTR 0x004 +#define GIC_DIST_IGROUP 0x080 +#define GIC_DIST_ENABLE_SET 0x100 +#define GIC_DIST_ENABLE_CLEAR 0x180 +#define GIC_DIST_PENDING_SET 0x200 +#define GIC_DIST_PENDING_CLEAR 0x280 +#define GIC_DIST_ACTIVE_SET 0x300 +#define GIC_DIST_ACTIVE_CLEAR 0x380 +#define GIC_DIST_PRI 0x400 +#define GIC_DIST_TARGET 0x800 +#define GIC_DIST_CONFIG 0xc00 +#define GIC_DIST_SOFTINT 0xf00 +#define GIC_DIST_SGI_PENDING_CLEAR 0xf10 +#define GIC_DIST_SGI_PENDING_SET 0xf20 + +#define GICD_ENABLE 0x1 +#define GICD_DISABLE 0x0 +#define GICD_INT_ACTLOW_LVLTRIG 0x0 +#define GICD_INT_EN_CLR_X32 0xffffffff +#define GICD_INT_EN_SET_SGI 0x0000ffff +#define GICD_INT_EN_CLR_PPI 0xffff0000 +#define GICD_INT_DEF_PRI 0xa0 +#define GICD_INT_DEF_PRI_X4 ((GICD_INT_DEF_PRI << 24) |\ + (GICD_INT_DEF_PRI << 16) |\ + (GICD_INT_DEF_PRI << 8) |\ + GICD_INT_DEF_PRI) + +#define GICH_HCR 0x0 +#define GICH_VTR 0x4 +#define GICH_VMCR 0x8 +#define GICH_MISR 0x10 +#define GICH_EISR0 0x20 +#define GICH_EISR1 0x24 +#define GICH_ELRSR0 0x30 +#define GICH_ELRSR1 0x34 +#define GICH_APR 0xf0 +#define GICH_LR0 0x100 + +#define GICH_HCR_EN (1 << 0) +#define GICH_HCR_UIE (1 << 1) + +#define GICH_LR_VIRTUALID (0x3ff << 0) +#define GICH_LR_PHYSID_CPUID_SHIFT (10) +#define GICH_LR_PHYSID_CPUID (7 << GICH_LR_PHYSID_CPUID_SHIFT) +#define GICH_LR_STATE (3 << 28) +#define GICH_LR_PENDING_BIT (1 << 28) +#define GICH_LR_ACTIVE_BIT (1 << 29) +#define GICH_LR_EOI (1 << 19) + +#define GICH_VMCR_CTRL_SHIFT 0 +#define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT) +#define GICH_VMCR_PRIMASK_SHIFT 27 +#define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT) +#define GICH_VMCR_BINPOINT_SHIFT 21 +#define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT) +#define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18 +#define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT) + +#define GICH_MISR_EOI (1 << 0) +#define GICH_MISR_U (1 << 1) + +#ifndef __ASSEMBLY__ +#include + +#define GIC_DIST_BASE (gicv2_data.dist_base) +#define GIC_CPU_BASE (gicv2_data.cpu_base) + +struct gicv2_data { + void *dist_base; + void *cpu_base; +}; + +extern struct gicv2_data gicv2_data; + +static inline void gic_enable(void) +{ + writel(GICD_ENABLE, GIC_DIST_BASE + GIC_DIST_CTRL); + writel(0xff, GIC_CPU_BASE + GIC_CPU_PRIMASK); + writel(GICC_ENABLE, GIC_CPU_BASE + GIC_CPU_CTRL); +} + +static inline void gic_irq_ack(void) +{ + unsigned int iar = readl(GIC_CPU_BASE + GIC_CPU_INTACK); + writel(iar, GIC_CPU_BASE + GIC_CPU_EOI); +} + +static inline void gic_send_sgi(unsigned int cpu, unsigned int irq) +{ + writel(((1 << cpu) << 16) | irq, GIC_DIST_BASE + GIC_DIST_SOFTINT); +} + +#endif /* !__ASSEMBLY__ */ +#endif /* _ASMARM_GIC_H_ */ diff --git a/lib/arm/io.c b/lib/arm/io.c index a08d394..9eae13f 100644 --- a/lib/arm/io.c +++ b/lib/arm/io.c @@ -12,6 +12,7 @@ #include #include #include +#include #include extern void halt(int code); @@ -62,10 +63,40 @@ static void uart0_init(void) } } +struct gicv2_data gicv2_data; +static int gicv2_init(void) +{ + const char *compatible = "arm,cortex-a15-gic"; + struct dt_pbus_reg reg; + struct dt_device gic; + struct dt_bus bus; + int node; + + dt_bus_init_defaults(&bus); + dt_device_init(&gic, &bus, NULL); + + node = dt_device_find_compatible(&gic, compatible); + assert(node >= 0 || node == -FDT_ERR_NOTFOUND); + + if (node == -FDT_ERR_NOTFOUND) + return node; + + assert(dt_pbus_translate_node(node, 0, ®) == 0); + + gicv2_data.dist_base = ioremap(reg.addr, reg.size); + + assert(dt_pbus_translate_node(node, 1, ®) == 0); + + gicv2_data.cpu_base = ioremap(reg.addr, reg.size); + + return 0; +} + void io_init(void) { uart0_init(); chr_testdev_init(); + assert(gicv2_init() == 0); } void puts(const char *s) diff --git a/lib/arm64/asm/gic.h b/lib/arm64/asm/gic.h new file mode 100644 index 0000000..e5eb302 --- /dev/null +++ b/lib/arm64/asm/gic.h @@ -0,0 +1 @@ +#include "../../arm/asm/gic.h"