From patchwork Thu Feb 18 19:31:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laszlo Ersek X-Patchwork-Id: 62238 Delivered-To: patch@linaro.org Received: by 10.112.43.199 with SMTP id y7csp769158lbl; Thu, 18 Feb 2016 11:31:54 -0800 (PST) X-Received: by 10.55.22.211 with SMTP id 80mr10846383qkw.63.1455823914144; Thu, 18 Feb 2016 11:31:54 -0800 (PST) Return-Path: Received: from lists.gnu.org (lists.gnu.org. [2001:4830:134:3::11]) by mx.google.com with ESMTPS id f81si9529761qkb.82.2016.02.18.11.31.53 for (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 18 Feb 2016 11:31:54 -0800 (PST) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:44762 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWUIr-0000cb-Lb for patch@linaro.org; Thu, 18 Feb 2016 14:31:53 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38189) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWUIE-0008Ih-9Q for qemu-devel@nongnu.org; Thu, 18 Feb 2016 14:31:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aWUI7-0007F7-Na for qemu-devel@nongnu.org; Thu, 18 Feb 2016 14:31:14 -0500 Received: from mx1.redhat.com ([209.132.183.28]:38780) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWUI7-0007Er-Fd; Thu, 18 Feb 2016 14:31:07 -0500 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) by mx1.redhat.com (Postfix) with ESMTPS id BB23F8E706; Thu, 18 Feb 2016 19:31:06 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-113-20.phx2.redhat.com [10.3.113.20]) by int-mx13.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u1IJV4Se011799; Thu, 18 Feb 2016 14:31:04 -0500 From: Laszlo Ersek To: qemu-devel@nongnu.org Date: Thu, 18 Feb 2016 20:31:00 +0100 Message-Id: <1455823860-22268-1-git-send-email-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.26 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: =?UTF-8?q?Marc=20Mar=ED?= , Gerd Hoffmann , Alexandre DERUMIER , qemu-stable@nongnu.org Subject: [Qemu-devel] [PATCH] fw_cfg: unbreak migration compatibility for 2.4 and earlier machines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When I reviewed Marc's fw_cfg DMA patches, I completely missed that the way we set dma_enabled would break migration. Gerd explained the right way (see reference below): dma_enabled should be set to true by default, and only true->false transitions should be possible: - when the user requests that with -global fw_cfg_mem.dma_enabled=off or -global fw_cfg_io.dma_enabled=off as appropriate for the platform, - when HW_COMPAT_2_4 dictates it, - when board code initializes fw_cfg without requesting DMA support. Cc: Marc Marí Cc: Gerd Hoffmann Cc: Alexandre DERUMIER Cc: qemu-stable@nongnu.org Ref: http://thread.gmane.org/gmane.comp.emulators.qemu/390272/focus=391042 Ref: https://bugs.launchpad.net/qemu/+bug/1536487 Suggested-by: Gerd Hoffmann Signed-off-by: Laszlo Ersek --- Notes: Tested the following cases with gdb, using qemu-system-x86_64, setting a breakpoint on (s->dma_enabled) in fw_cfg_init_io_dma(): * no special params (DMA enabled) * -global fw_cfg_io.dma_enabled=off (DMA disabled) * -M pc-i440fx-2.4 (DMA disabled), similarly with 2.3 and Q35 too Also tested the memory mapped case in practice, using qemu-system-aarch64 -M virt, -kernel / -initrd / -append, with guest UEFI: * no special params (DMA enabled) * -global fw_cfg_mem.dma_enabled=off (DMA disabled) Not tested: * actual migration * when board code doesn't request DMA support Testing feedback from people who use migration would be nice. include/hw/compat.h | 8 ++++++++ hw/nvram/fw_cfg.c | 20 ++++++++++++-------- 2 files changed, 20 insertions(+), 8 deletions(-) -- 1.8.3.1 diff --git a/include/hw/compat.h b/include/hw/compat.h index 2ebe739fcb5c..a5dbbf8984b1 100644 --- a/include/hw/compat.h +++ b/include/hw/compat.h @@ -42,6 +42,14 @@ .driver = "virtio-pci",\ .property = "migrate-extra",\ .value = "off",\ + },{\ + .driver = "fw_cfg_mem",\ + .property = "dma_enabled",\ + .value = "off",\ + },{\ + .driver = "fw_cfg_io",\ + .property = "dma_enabled",\ + .value = "off",\ }, #define HW_COMPAT_2_3 \ diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 79c5742b3362..f3acb47bd4dc 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -778,17 +778,19 @@ FWCfgState *fw_cfg_init_io_dma(uint32_t iobase, uint32_t dma_iobase, DeviceState *dev; FWCfgState *s; uint32_t version = FW_CFG_VERSION; - bool dma_enabled = dma_iobase && dma_as; + bool dma_requested = dma_iobase && dma_as; dev = qdev_create(NULL, TYPE_FW_CFG_IO); qdev_prop_set_uint32(dev, "iobase", iobase); qdev_prop_set_uint32(dev, "dma_iobase", dma_iobase); - qdev_prop_set_bit(dev, "dma_enabled", dma_enabled); + if (!dma_requested) { + qdev_prop_set_bit(dev, "dma_enabled", false); + } fw_cfg_init1(dev); s = FW_CFG(dev); - if (dma_enabled) { + if (s->dma_enabled) { /* 64 bits for the address field */ s->dma_as = dma_as; s->dma_addr = 0; @@ -814,11 +816,13 @@ FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, SysBusDevice *sbd; FWCfgState *s; uint32_t version = FW_CFG_VERSION; - bool dma_enabled = dma_addr && dma_as; + bool dma_requested = dma_addr && dma_as; dev = qdev_create(NULL, TYPE_FW_CFG_MEM); qdev_prop_set_uint32(dev, "data_width", data_width); - qdev_prop_set_bit(dev, "dma_enabled", dma_enabled); + if (!dma_requested) { + qdev_prop_set_bit(dev, "dma_enabled", false); + } fw_cfg_init1(dev); @@ -828,7 +832,7 @@ FWCfgState *fw_cfg_init_mem_wide(hwaddr ctl_addr, s = FW_CFG(dev); - if (dma_enabled) { + if (s->dma_enabled) { s->dma_as = dma_as; s->dma_addr = 0; sysbus_mmio_map(sbd, 2, dma_addr); @@ -873,7 +877,7 @@ static Property fw_cfg_io_properties[] = { DEFINE_PROP_UINT32("iobase", FWCfgIoState, iobase, -1), DEFINE_PROP_UINT32("dma_iobase", FWCfgIoState, dma_iobase, -1), DEFINE_PROP_BOOL("dma_enabled", FWCfgIoState, parent_obj.dma_enabled, - false), + true), DEFINE_PROP_END_OF_LIST(), }; @@ -913,7 +917,7 @@ static const TypeInfo fw_cfg_io_info = { static Property fw_cfg_mem_properties[] = { DEFINE_PROP_UINT32("data_width", FWCfgMemState, data_width, -1), DEFINE_PROP_BOOL("dma_enabled", FWCfgMemState, parent_obj.dma_enabled, - false), + true), DEFINE_PROP_END_OF_LIST(), };