From patchwork Tue Nov 24 11:18:43 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 57221 Delivered-To: patches@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp2017046lbb; Tue, 24 Nov 2015 03:18:44 -0800 (PST) X-Received: by 10.194.186.170 with SMTP id fl10mr34775697wjc.91.1448363924501; Tue, 24 Nov 2015 03:18:44 -0800 (PST) Return-Path: Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id w189si2580435wmd.3.2015.11.24.03.18.44 for (version=TLS1_2 cipher=AES128-SHA bits=128/128); Tue, 24 Nov 2015 03:18:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1a1BcR-0002f4-LP; Tue, 24 Nov 2015 11:18:43 +0000 From: Peter Maydell --from=Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, qemu-arm@nongnu.org, Laurent Desnogues , Sergey Fedorov Subject: [PATCH v2 for-2.5] target-arm/translate-a64.c: Correct unallocated checks for ldst_excl Date: Tue, 24 Nov 2015 11:18:43 +0000 Message-Id: <1448363923-10205-1-git-send-email-pmaydell@chiark.greenend.org.uk> X-Mailer: git-send-email 1.7.10.4 From: Peter Maydell The checks for the unallocated encodings in the ldst_excl group (exclusives and load-acquire/store-release) were not correct. This error meant that in turn we ended up with code attempting to handle the non-existent case of "non-exclusive load-acquire/store-release pair". Delete that broken and now unreachable code. Reported-by: Laurent Desnogues Signed-off-by: Peter Maydell --- The easiest way to validate that we have the unallocated conditions correct now is to look at C4.4.6 "load/store exclusive" in the v8 ARM ARM rev A.3h: our three conditions correspond to the three "unallocated" rows in the decode table. v2 changes: remove incorrect comment too. --- target-arm/translate-a64.c | 15 ++------------- 1 file changed, 2 insertions(+), 13 deletions(-) -- 1.9.1 diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index fe485a4..14e8131 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1816,9 +1816,6 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, * o2: 0 -> exclusive, 1 -> not * o1: 0 -> single register, 1 -> register pair * o0: 1 -> load-acquire/store-release, 0 -> not - * - * o0 == 0 AND o2 == 1 is un-allocated - * o1 == 1 is un-allocated except for 32 and 64 bit sizes */ static void disas_ldst_excl(DisasContext *s, uint32_t insn) { @@ -1833,7 +1830,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) int size = extract32(insn, 30, 2); TCGv_i64 tcg_addr; - if ((!is_excl && !is_lasr) || + if ((!is_excl && !is_pair && !is_lasr) || + (!is_excl && is_pair) || (is_pair && size < 2)) { unallocated_encoding(s); return; @@ -1862,15 +1860,6 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) } else { do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false); } - if (is_pair) { - TCGv_i64 tcg_rt2 = cpu_reg(s, rt); - tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); - if (is_store) { - do_gpr_st(s, tcg_rt2, tcg_addr, size); - } else { - do_gpr_ld(s, tcg_rt2, tcg_addr, size, false, false); - } - } } }