From patchwork Mon Nov 16 14:05:23 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 56637 Delivered-To: patches@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp1334493lbb; Mon, 16 Nov 2015 06:05:25 -0800 (PST) X-Received: by 10.25.136.213 with SMTP id k204mr17012342lfd.101.1447682725947; Mon, 16 Nov 2015 06:05:25 -0800 (PST) Return-Path: Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id je8si855566lbc.172.2015.11.16.06.05.25 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 16 Nov 2015 06:05:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZyKPM-00013q-5p; Mon, 16 Nov 2015 14:05:24 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , "Edgar E. Iglesias" , Paolo Bonzini , =?UTF-8?q?Andreas=20F=C3=A4rber?= , qemu-arm@nongnu.org Subject: [PATCH v2 19/19] HACK: rearrange the virt memory map to suit OP-TEE Date: Mon, 16 Nov 2015 14:05:23 +0000 Message-Id: <1447682723-3977-20-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1447682723-3977-1-git-send-email-peter.maydell@linaro.org> References: <1447682723-3977-1-git-send-email-peter.maydell@linaro.org> The current OP-TEE codebase expects the secure UART to be at 0x09010000 and irq 2 (it is based on an old non-upstream patch to add a second uart, and upstream used that memory map area for something else). When the TZ support is upstream in QEMU we can move OP-TEE on to a proper upstream QEMU and update it to use the new UART location, but for now this hack patch allows running a more-or-less unmodified OP-TEE. Put the secure UART at the address and irq where OP-TEE expects it, moving some other devices down to make space. Signed-off-by: Peter Maydell --- hw/arm/virt.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) -- 1.9.1 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 623e835..ced42be 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -118,9 +118,9 @@ static const MemMapEntry a15memmap[] = { /* This redistributor space allows up to 2*64kB*123 CPUs */ [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 }, [VIRT_UART] = { 0x09000000, 0x00001000 }, - [VIRT_RTC] = { 0x09010000, 0x00001000 }, - [VIRT_FW_CFG] = { 0x09020000, 0x00000018 }, - [VIRT_SECURE_UART] = { 0x09030000, 0x00001000 }, + [VIRT_RTC] = { 0x09020000, 0x00001000 }, + [VIRT_FW_CFG] = { 0x09030000, 0x00000018 }, + [VIRT_SECURE_UART] = { 0x09010000, 0x00001000 }, [VIRT_MMIO] = { 0x0a000000, 0x00000200 }, /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */ [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 }, @@ -134,9 +134,9 @@ static const MemMapEntry a15memmap[] = { static const int a15irqmap[] = { [VIRT_UART] = 1, - [VIRT_RTC] = 2, - [VIRT_PCIE] = 3, /* ... to 6 */ - [VIRT_SECURE_UART] = 7, + [VIRT_RTC] = 3, + [VIRT_PCIE] = 4, /* ... to 7 */ + [VIRT_SECURE_UART] = 2, [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */ [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */