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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id q67si37378972qgd.55.2015.10.27.07.40.25 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 27 Oct 2015 07:40:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Authentication-Results: mx.google.com; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) smtp.mailfrom=qemu-devel-bounces+patch=linaro.org@nongnu.org Received: from localhost ([::1]:60081 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zr5QH-0004jn-7m for patch@linaro.org; Tue, 27 Oct 2015 10:40:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56969) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zr5Jn-0001jP-2w for qemu-devel@nongnu.org; Tue, 27 Oct 2015 10:33:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Zr5Je-0007WB-51 for qemu-devel@nongnu.org; Tue, 27 Oct 2015 10:33:42 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:35203) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Zr5Jd-0007SU-TC for qemu-devel@nongnu.org; Tue, 27 Oct 2015 10:33:34 -0400 Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1Zr5JZ-0000UL-NL for qemu-devel@nongnu.org; Tue, 27 Oct 2015 14:33:29 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 27 Oct 2015 14:33:09 +0000 Message-Id: <1445956409-1818-8-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1445956409-1818-1-git-send-email-peter.maydell@linaro.org> References: <1445956409-1818-1-git-send-email-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Error: Malformed IPv6 address (bad octet value). X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 07/27] i.MX: Standardize i.MX GPIO debug X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Jean-Christophe Dubois The goal is to have debug code always compiled during build. We standardize all debug output on the following format: [QOM_TYPE_NAME]reporting_function: debug message The qemu_log_mask() outputis following the same format as the above debug. Reviewed-by: Peter Crosthwaite Signed-off-by: Jean-Christophe Dubois Message-id: 4f2007adcf0f579864bb4dd8a825824e0e9098b8.1445781957.git.jcd@tribudubois.net Signed-off-by: Peter Maydell --- hw/gpio/imx_gpio.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) -- 1.9.1 diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c index d56ffcd..3170585 100644 --- a/hw/gpio/imx_gpio.c +++ b/hw/gpio/imx_gpio.c @@ -29,11 +29,12 @@ typedef enum IMXGPIOLevel { } IMXGPIOLevel; #define DPRINTF(fmt, args...) \ - do { \ - if (DEBUG_IMX_GPIO) { \ - fprintf(stderr, "%s: " fmt , __func__, ##args); \ - } \ - } while (0) + do { \ + if (DEBUG_IMX_GPIO) { \ + fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPIO, \ + __func__, ##args); \ + } \ + } while (0) static const char *imx_gpio_reg_name(uint32_t reg) { @@ -176,19 +177,19 @@ static uint64_t imx_gpio_read(void *opaque, hwaddr offset, unsigned size) if (s->has_edge_sel) { reg_value = s->edge_sel; } else { - qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: EDGE_SEL register not " + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not " "present on this version of GPIO device\n", TYPE_IMX_GPIO, __func__); } break; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad register at offset %d\n", - TYPE_IMX_GPIO, __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" + HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset); break; } - DPRINTF("(%s) = 0x%"PRIx32"\n", imx_gpio_reg_name(offset), reg_value); + DPRINTF("(%s) = 0x%" PRIx32 "\n", imx_gpio_reg_name(offset), reg_value); return reg_value; } @@ -198,7 +199,7 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value, { IMXGPIOState *s = IMX_GPIO(opaque); - DPRINTF("(%s, value = 0x%"PRIx32")\n", imx_gpio_reg_name(offset), + DPRINTF("(%s, value = 0x%" PRIx32 ")\n", imx_gpio_reg_name(offset), (uint32_t)value); switch (offset) { @@ -238,15 +239,15 @@ static void imx_gpio_write(void *opaque, hwaddr offset, uint64_t value, s->edge_sel = value; imx_gpio_set_all_int_lines(s); } else { - qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: EDGE_SEL register not " + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: EDGE_SEL register not " "present on this version of GPIO device\n", TYPE_IMX_GPIO, __func__); } break; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s[%s]: Bad register at offset %d\n", - TYPE_IMX_GPIO, __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" + HWADDR_PRIx "\n", TYPE_IMX_GPIO, __func__, offset); break; }