From patchwork Mon Oct 26 18:12:58 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 55573 Delivered-To: patches@linaro.org Received: by 10.112.59.35 with SMTP id w3csp1347348lbq; Mon, 26 Oct 2015 11:13:01 -0700 (PDT) X-Received: by 10.194.209.175 with SMTP id mn15mr22456424wjc.22.1445883180510; Mon, 26 Oct 2015 11:13:00 -0700 (PDT) Return-Path: Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id g7si44587562wjx.122.2015.10.26.11.12.59 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 26 Oct 2015 11:13:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZqmGQ-00009s-RG; Mon, 26 Oct 2015 18:12:58 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , "Edgar E. Iglesias" Subject: [PATCH for-2.5 2/2] target-arm: Report S/NS status in the CPU debug logs Date: Mon, 26 Oct 2015 18:12:58 +0000 Message-Id: <1445883178-576-3-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1445883178-576-1-git-send-email-peter.maydell@linaro.org> References: <1445883178-576-1-git-send-email-peter.maydell@linaro.org> If this CPU supports EL3, enhance the printing of the current CPU mode in debug logging to distinguish S from NS modes as appropriate. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 11 ++++++++++- target-arm/translate.c | 12 +++++++++++- 2 files changed, 21 insertions(+), 2 deletions(-) -- 1.9.1 Reviewed-by: Alex Bennée diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index ccefa7b..8ebdcb7 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -127,6 +127,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, uint32_t psr = pstate_read(env); int i; int el = arm_current_el(env); + const char *ns_status; cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", env->pc, env->xregs[31]); @@ -138,12 +139,20 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, cpu_fprintf(f, " "); } } - cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c EL%d%c\n", + + if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { + ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + } else { + ns_status = ""; + } + + cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n", psr, psr & PSTATE_N ? 'N' : '-', psr & PSTATE_Z ? 'Z' : '-', psr & PSTATE_C ? 'C' : '-', psr & PSTATE_V ? 'V' : '-', + ns_status, el, psr & PSTATE_SP ? 'h' : 't'); diff --git a/target-arm/translate.c b/target-arm/translate.c index 9f1d740..5f2346a 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11556,6 +11556,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, CPUARMState *env = &cpu->env; int i; uint32_t psr; + const char *ns_status; if (is_a64(env)) { aarch64_cpu_dump_state(cs, f, cpu_fprintf, flags); @@ -11570,13 +11571,22 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, cpu_fprintf(f, " "); } psr = cpsr_read(env); - cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%d\n", + + if (arm_feature(env, ARM_FEATURE_EL3) && + (psr & CPSR_M) != ARM_CPU_MODE_MON) { + ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; + } else { + ns_status = ""; + } + + cpu_fprintf(f, "PSR=%08x %c%c%c%c %c %s%s%d\n", psr, psr & (1 << 31) ? 'N' : '-', psr & (1 << 30) ? 'Z' : '-', psr & (1 << 29) ? 'C' : '-', psr & (1 << 28) ? 'V' : '-', psr & CPSR_T ? 'T' : 'A', + ns_status, cpu_mode_names[psr & 0xf], (psr & 0x10) ? 32 : 26); if (flags & CPU_DUMP_FPU) {