From patchwork Mon Oct 26 18:12:57 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 55574 Delivered-To: patches@linaro.org Received: by 10.112.59.35 with SMTP id w3csp1347376lbq; Mon, 26 Oct 2015 11:13:03 -0700 (PDT) X-Received: by 10.25.39.76 with SMTP id n73mr11460037lfn.60.1445883180645; Mon, 26 Oct 2015 11:13:00 -0700 (PDT) Return-Path: Received: from mnementh.archaic.org.uk (mnementh.archaic.org.uk. [2001:8b0:1d0::1]) by mx.google.com with ESMTPS id n187si21675218lfb.31.2015.10.26.11.13.00 (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Mon, 26 Oct 2015 11:13:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) client-ip=2001:8b0:1d0::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of pm215@archaic.org.uk designates 2001:8b0:1d0::1 as permitted sender) smtp.mailfrom=pm215@archaic.org.uk Received: from pm215 by mnementh.archaic.org.uk with local (Exim 4.80) (envelope-from ) id 1ZqmGQ-00009o-Q5; Mon, 26 Oct 2015 18:12:58 +0000 From: Peter Maydell To: qemu-devel@nongnu.org Cc: patches@linaro.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , "Edgar E. Iglesias" Subject: [PATCH for-2.5 1/2] target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32 Date: Mon, 26 Oct 2015 18:12:57 +0000 Message-Id: <1445883178-576-2-git-send-email-peter.maydell@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1445883178-576-1-git-send-email-peter.maydell@linaro.org> References: <1445883178-576-1-git-send-email-peter.maydell@linaro.org> The AArch64 debug CPU display of PSTATE as "PSTATE=200003c5 (flags --C-)" on the end of the same line as the last of the general purpose registers is unnecessarily different from the AArch32 display of PSR as "PSR=200001d3 --C- A svc32" on its own line. Update the AArch64 code to put PSTATE in its own line and in the same format, including printing the exception level (mode). Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) -- 1.9.1 Reviewed-by: Alex Bennée diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 19f9d8d..ccefa7b 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -126,6 +126,7 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, CPUARMState *env = &cpu->env; uint32_t psr = pstate_read(env); int i; + int el = arm_current_el(env); cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", env->pc, env->xregs[31]); @@ -137,13 +138,14 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, cpu_fprintf(f, " "); } } - cpu_fprintf(f, "PSTATE=%08x (flags %c%c%c%c)\n", + cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c EL%d%c\n", psr, psr & PSTATE_N ? 'N' : '-', psr & PSTATE_Z ? 'Z' : '-', psr & PSTATE_C ? 'C' : '-', - psr & PSTATE_V ? 'V' : '-'); - cpu_fprintf(f, "\n"); + psr & PSTATE_V ? 'V' : '-', + el, + psr & PSTATE_SP ? 'h' : 't'); if (flags & CPU_DUMP_FPU) { int numvfpregs = 32;