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[2001:4830:134:3::11]) by mx.google.com with ESMTPS id y94si28660499qge.48.2015.10.06.07.38.58 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Tue, 06 Oct 2015 07:38:59 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 2001:4830:134:3::11 as permitted sender) client-ip=2001:4830:134:3::11; Received: from localhost ([::1]:52063 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjTOM-00072P-P0 for patch@linaro.org; Tue, 06 Oct 2015 10:38:58 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40590) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjTMn-0006CM-S3 for qemu-devel@nongnu.org; Tue, 06 Oct 2015 10:37:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ZjTMi-0000fc-9B for qemu-devel@nongnu.org; Tue, 06 Oct 2015 10:37:21 -0400 Received: from mx1.redhat.com ([209.132.183.28]:55608) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ZjTMh-0000fE-Rv for qemu-devel@nongnu.org; Tue, 06 Oct 2015 10:37:16 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) by mx1.redhat.com (Postfix) with ESMTPS id 55099344F5C; Tue, 6 Oct 2015 14:37:15 +0000 (UTC) Received: from hawk.localdomain.com (dhcp-1-123.brq.redhat.com [10.34.1.123]) by int-mx14.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id t96EbBsU004599; Tue, 6 Oct 2015 10:37:14 -0400 From: Andrew Jones To: qemu-devel@nongnu.org Date: Tue, 6 Oct 2015 16:37:07 +0200 Message-Id: <1444142228-6696-2-git-send-email-drjones@redhat.com> In-Reply-To: <1444142228-6696-1-git-send-email-drjones@redhat.com> References: <1444142228-6696-1-git-send-email-drjones@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.27 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 209.132.183.28 Cc: peter.maydell@linaro.org, p.fedin@samsung.com, afaerber@suse.de Subject: [Qemu-devel] [PATCH 1/2] [RFC] arm_gic_common.h: add gicv2 aliases for defines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: drjones@redhat.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.175 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 I'm not sure if arm_gic_common.h is supposed to be common, not only between tcg and kvm, but also v2 and v3, but it currently is (arm_gicv3_common.h includes it, and it's the only gic header included by hw/arm/virt.c). If it should be the super-common header, then it's unfortunate that the define names are too generic. This patch doesn't help much, as it doesn't rename anything, but it does start heading down the right path. With it, code including the super-common header can start using more appropriate names for a couple very gic-version-specific defines. Signed-off-by: Andrew Jones --- include/hw/intc/arm_gic_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h index 564a72b2cf77f..299226064a30f 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -25,11 +25,13 @@ /* Maximum number of possible interrupts, determined by the GIC architecture */ #define GIC_MAXIRQ 1020 +#define GICV2_MAXIRQ GIC_MAXIRQ /* First 32 are private to each CPU (SGIs and PPIs). */ #define GIC_INTERNAL 32 #define GIC_NR_SGIS 16 /* Maximum number of possible CPU interfaces, determined by GIC architecture */ #define GIC_NCPU 8 +#define GICV2_NCPU GIC_NCPU #define MAX_NR_GROUP_PRIO 128 #define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)