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X-Received-From: 2001:8b0:1d0::1 Subject: [Qemu-devel] [PULL 11/24] target-arm: Eliminate unnecessary zero-extend in disas_bitfield X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: peter.maydell@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.41 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 From: Richard Henderson For !SF, this initial ext32u can't be optimized away by the current TCG code generator. (It would require backward bit liveness propagation.) But since the range of bits for !SF are already constrained by unallocated_encoding, we'll never reference the high bits anyway. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 1441909103-24666-10-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index f2f8443..3ab0b42 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -3015,7 +3015,11 @@ static void disas_bitfield(DisasContext *s, uint32_t insn) } tcg_rd = cpu_reg(s, rd); - tcg_tmp = read_cpu_reg(s, rn, sf); + + /* Suppress the zero-extend for !sf. Since RI and SI are constrained + to be smaller than bitsize, we'll never reference data outside the + low 32-bits anyway. */ + tcg_tmp = read_cpu_reg(s, rn, 1); /* Recognize the common aliases. */ if (opc == 0) { /* SBFM */